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| 1 | +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| 2 | +%YAML 1.2 |
| 3 | +--- |
| 4 | +$id: http://devicetree.org/schemas/clock/arm,syscon-icst.yaml# |
| 5 | +$schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | + |
| 7 | +title: ARM System Controller ICST Clocks |
| 8 | + |
| 9 | +maintainers: |
| 10 | + - Linus Walleij <[email protected]> |
| 11 | + |
| 12 | +description: | |
| 13 | + The ICS525 and ICS307 oscillators are produced by Integrated |
| 14 | + Devices Technology (IDT). ARM integrated these oscillators deeply into their |
| 15 | + reference designs by adding special control registers that manage such |
| 16 | + oscillators to their system controllers. |
| 17 | +
|
| 18 | + The various ARM system controllers contain logic to serialize and initialize |
| 19 | + an ICST clock request after a write to the 32 bit register at an offset |
| 20 | + into the system controller. Furthermore, to even be able to alter one of |
| 21 | + these frequencies, the system controller must first be unlocked by |
| 22 | + writing a special token to another offset in the system controller. |
| 23 | +
|
| 24 | + Some ARM hardware contain special versions of the serial interface that only |
| 25 | + connects the low 8 bits of the VDW (missing one bit), hard-wires RDW to |
| 26 | + different values and sometimes also hard-wires the output divider. They |
| 27 | + therefore have special compatible strings as per this table (the OD value is |
| 28 | + the value on the pins, not the resulting output divider). |
| 29 | +
|
| 30 | + In the core modules and logic tiles, the ICST is a configurable clock fed |
| 31 | + from a 24 MHz clock on the motherboard (usually the main crystal) used for |
| 32 | + generating e.g. video clocks. It is located on the core module and there is |
| 33 | + only one of these. This clock node must be a subnode of the core module. |
| 34 | +
|
| 35 | + Hardware variant RDW OD VDW |
| 36 | +
|
| 37 | + Integrator/AP 22 1 Bit 8 0, rest variable |
| 38 | + integratorap-cm |
| 39 | +
|
| 40 | + Integrator/AP 46 3 Bit 8 0, rest variable |
| 41 | + integratorap-sys |
| 42 | +
|
| 43 | + Integrator/AP 22 or 1 17 or (33 or 25 MHz) |
| 44 | + integratorap-pci 14 1 14 |
| 45 | +
|
| 46 | + Integrator/CP 22 variable Bit 8 0, rest variable |
| 47 | + integratorcp-cm-core |
| 48 | +
|
| 49 | + Integrator/CP 22 variable Bit 8 0, rest variable |
| 50 | + integratorcp-cm-mem |
| 51 | +
|
| 52 | + The ICST oscillator must be provided inside a system controller node. |
| 53 | +
|
| 54 | +properties: |
| 55 | + "#clock-cells": |
| 56 | + const: 0 |
| 57 | + |
| 58 | + compatible: |
| 59 | + enum: |
| 60 | + - arm,syscon-icst525 |
| 61 | + - arm,syscon-icst307 |
| 62 | + - arm,syscon-icst525-integratorap-cm |
| 63 | + - arm,syscon-icst525-integratorap-sys |
| 64 | + - arm,syscon-icst525-integratorap-pci |
| 65 | + - arm,syscon-icst525-integratorcp-cm-core |
| 66 | + - arm,syscon-icst525-integratorcp-cm-mem |
| 67 | + - arm,integrator-cm-auxosc |
| 68 | + - arm,versatile-cm-auxosc |
| 69 | + - arm,impd-vco1 |
| 70 | + - arm,impd-vco2 |
| 71 | + |
| 72 | + clocks: |
| 73 | + description: Parent clock for the ICST VCO |
| 74 | + maxItems: 1 |
| 75 | + |
| 76 | + clock-output-names: |
| 77 | + maxItems: 1 |
| 78 | + |
| 79 | + lock-offset: |
| 80 | + $ref: '/schemas/types.yaml#/definitions/uint32' |
| 81 | + description: Offset to the unlocking register for the oscillator |
| 82 | + |
| 83 | + vco-offset: |
| 84 | + $ref: '/schemas/types.yaml#/definitions/uint32' |
| 85 | + description: Offset to the VCO register for the oscillator |
| 86 | + |
| 87 | +required: |
| 88 | + - "#clock-cells" |
| 89 | + - compatible |
| 90 | + - clocks |
| 91 | + |
| 92 | +examples: |
| 93 | + - | |
| 94 | + vco1: clock@00 { |
| 95 | + compatible = "arm,impd1-vco1"; |
| 96 | + #clock-cells = <0>; |
| 97 | + lock-offset = <0x08>; |
| 98 | + vco-offset = <0x00>; |
| 99 | + clocks = <&sysclk>; |
| 100 | + clock-output-names = "IM-PD1-VCO1"; |
| 101 | + }; |
| 102 | +
|
| 103 | +... |
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