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drm/i915/gt: Use RC6 residency types as arguments to residency functions
Previously RC6 residency functions directly accepted RC6 residency register MMIO offsets (there are four RC6 residency registers). This worked but required an assumption on the residency register layout so was not future proof. Therefore change RC6 residency functions to accept RC6 residency types instead of register MMIO offsets. The knowledge of register offsets as well as ID to offset mapping is now maintained solely in intel_rc6 and can be tailored for different platforms and different register layouts as need arises. v2: Address review comments by Jani N - Change residency functions to accept RC6 residency types instead of register ID's - s/intel_rc6_print_rc5_res/intel_rc6_print_residency/ - Remove "const enum" in function arguments - Naming: intel_rc6_* for enum - Use INTEL_RC6_RES_MAX and other minor changes v3: Don't include intel_rc6_types.h in intel_rc6.h (Jani) Suggested-by: Rodrigo Vivi <[email protected]> Suggested-by: Jani Nikula <[email protected]> Reported-by: Jani Nikula <[email protected]> Signed-off-by: Ashutosh Dixit <[email protected]> Reviewed-by: Rodrigo Vivi <[email protected]> Signed-off-by: Badal Nilawar <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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-60
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7 files changed

+72
-60
lines changed

‎drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c

Lines changed: 7 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -83,19 +83,6 @@ static int fw_domains_show(struct seq_file *m, void *data)
8383
}
8484
DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(fw_domains);
8585

86-
static void print_rc6_res(struct seq_file *m,
87-
const char *title,
88-
const i915_reg_t reg)
89-
{
90-
struct intel_gt *gt = m->private;
91-
intel_wakeref_t wakeref;
92-
93-
with_intel_runtime_pm(gt->uncore->rpm, wakeref)
94-
seq_printf(m, "%s %u (%llu us)\n", title,
95-
intel_uncore_read(gt->uncore, reg),
96-
intel_rc6_residency_us(&gt->rc6, reg));
97-
}
98-
9986
static int vlv_drpc(struct seq_file *m)
10087
{
10188
struct intel_gt *gt = m->private;
@@ -115,8 +102,8 @@ static int vlv_drpc(struct seq_file *m)
115102
seq_printf(m, "Media Power Well: %s\n",
116103
(pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
117104

118-
print_rc6_res(m, "Render RC6 residency since boot:", GEN6_GT_GFX_RC6);
119-
print_rc6_res(m, "Media RC6 residency since boot:", VLV_GT_MEDIA_RC6);
105+
intel_rc6_print_residency(m, "Render RC6 residency since boot:", INTEL_RC6_RES_RC6);
106+
intel_rc6_print_residency(m, "Media RC6 residency since boot:", INTEL_RC6_RES_VLV_MEDIA);
120107

121108
return fw_domains_show(m, NULL);
122109
}
@@ -192,11 +179,11 @@ static int gen6_drpc(struct seq_file *m)
192179
}
193180

194181
/* Not exactly sure what this is */
195-
print_rc6_res(m, "RC6 \"Locked to RPn\" residency since boot:",
196-
GEN6_GT_GFX_RC6_LOCKED);
197-
print_rc6_res(m, "RC6 residency since boot:", GEN6_GT_GFX_RC6);
198-
print_rc6_res(m, "RC6+ residency since boot:", GEN6_GT_GFX_RC6p);
199-
print_rc6_res(m, "RC6++ residency since boot:", GEN6_GT_GFX_RC6pp);
182+
intel_rc6_print_residency(m, "RC6 \"Locked to RPn\" residency since boot:",
183+
INTEL_RC6_RES_RC6_LOCKED);
184+
intel_rc6_print_residency(m, "RC6 residency since boot:", INTEL_RC6_RES_RC6);
185+
intel_rc6_print_residency(m, "RC6+ residency since boot:", INTEL_RC6_RES_RC6p);
186+
intel_rc6_print_residency(m, "RC6++ residency since boot:", INTEL_RC6_RES_RC6pp);
200187

201188
if (GRAPHICS_VER(i915) <= 7) {
202189
seq_printf(m, "RC6 voltage: %dmV\n",

‎drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -165,13 +165,13 @@ sysfs_gt_attribute_r_func(struct kobject *kobj, struct attribute *attr,
165165
INTEL_GT_ATTR_RO(_name)
166166

167167
#ifdef CONFIG_PM
168-
static u32 get_residency(struct intel_gt *gt, i915_reg_t reg)
168+
static u32 get_residency(struct intel_gt *gt, enum intel_rc6_res_type id)
169169
{
170170
intel_wakeref_t wakeref;
171171
u64 res = 0;
172172

173173
with_intel_runtime_pm(gt->uncore->rpm, wakeref)
174-
res = intel_rc6_residency_us(&gt->rc6, reg);
174+
res = intel_rc6_residency_us(&gt->rc6, id);
175175

176176
return DIV_ROUND_CLOSEST_ULL(res, 1000);
177177
}
@@ -210,22 +210,22 @@ static ssize_t rc6_enable_dev_show(struct device *dev,
210210

211211
static u32 __rc6_residency_ms_show(struct intel_gt *gt)
212212
{
213-
return get_residency(gt, GEN6_GT_GFX_RC6);
213+
return get_residency(gt, INTEL_RC6_RES_RC6);
214214
}
215215

216216
static u32 __rc6p_residency_ms_show(struct intel_gt *gt)
217217
{
218-
return get_residency(gt, GEN6_GT_GFX_RC6p);
218+
return get_residency(gt, INTEL_RC6_RES_RC6p);
219219
}
220220

221221
static u32 __rc6pp_residency_ms_show(struct intel_gt *gt)
222222
{
223-
return get_residency(gt, GEN6_GT_GFX_RC6pp);
223+
return get_residency(gt, INTEL_RC6_RES_RC6pp);
224224
}
225225

226226
static u32 __media_rc6_residency_ms_show(struct intel_gt *gt)
227227
{
228-
return get_residency(gt, VLV_GT_MEDIA_RC6);
228+
return get_residency(gt, INTEL_RC6_RES_VLV_MEDIA);
229229
}
230230

231231
INTEL_GT_SYSFS_SHOW_MIN(rc6_residency_ms);

‎drivers/gpu/drm/i915/gt/intel_rc6.c

Lines changed: 33 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -551,6 +551,14 @@ static void __intel_rc6_disable(struct intel_rc6 *rc6)
551551
intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
552552
}
553553

554+
static void rc6_res_reg_init(struct intel_rc6 *rc6)
555+
{
556+
rc6->res_reg[INTEL_RC6_RES_RC6_LOCKED] = GEN6_GT_GFX_RC6_LOCKED;
557+
rc6->res_reg[INTEL_RC6_RES_RC6] = GEN6_GT_GFX_RC6;
558+
rc6->res_reg[INTEL_RC6_RES_RC6p] = GEN6_GT_GFX_RC6p;
559+
rc6->res_reg[INTEL_RC6_RES_RC6pp] = GEN6_GT_GFX_RC6pp;
560+
}
561+
554562
void intel_rc6_init(struct intel_rc6 *rc6)
555563
{
556564
struct drm_i915_private *i915 = rc6_to_i915(rc6);
@@ -562,6 +570,8 @@ void intel_rc6_init(struct intel_rc6 *rc6)
562570
if (!rc6_supported(rc6))
563571
return;
564572

573+
rc6_res_reg_init(rc6);
574+
565575
if (IS_CHERRYVIEW(i915))
566576
err = chv_rc6_init(rc6);
567577
else if (IS_VALLEYVIEW(i915))
@@ -736,31 +746,19 @@ static u64 vlv_residency_raw(struct intel_uncore *uncore, const i915_reg_t reg)
736746
return lower | (u64)upper << 8;
737747
}
738748

739-
u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, const i915_reg_t reg)
749+
u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, enum intel_rc6_res_type id)
740750
{
741751
struct drm_i915_private *i915 = rc6_to_i915(rc6);
742752
struct intel_uncore *uncore = rc6_to_uncore(rc6);
743753
u64 time_hw, prev_hw, overflow_hw;
754+
i915_reg_t reg = rc6->res_reg[id];
744755
unsigned int fw_domains;
745756
unsigned long flags;
746-
unsigned int i;
747757
u32 mul, div;
748758

749759
if (!rc6->supported)
750760
return 0;
751761

752-
/*
753-
* Store previous hw counter values for counter wrap-around handling.
754-
*
755-
* There are only four interesting registers and they live next to each
756-
* other so we can use the relative address, compared to the smallest
757-
* one as the index into driver storage.
758-
*/
759-
i = (i915_mmio_reg_offset(reg) -
760-
i915_mmio_reg_offset(GEN6_GT_GFX_RC6_LOCKED)) / sizeof(u32);
761-
if (drm_WARN_ON_ONCE(&i915->drm, i >= ARRAY_SIZE(rc6->cur_residency)))
762-
return 0;
763-
764762
fw_domains = intel_uncore_forcewake_for_reg(uncore, reg, FW_REG_READ);
765763

766764
spin_lock_irqsave(&uncore->lock, flags);
@@ -789,11 +787,11 @@ u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, const i915_reg_t reg)
789787
/*
790788
* Counter wrap handling.
791789
*
792-
* But relying on a sufficient frequency of queries otherwise counters
793-
* can still wrap.
790+
* Store previous hw counter values for counter wrap-around handling. But
791+
* relying on a sufficient frequency of queries otherwise counters can still wrap.
794792
*/
795-
prev_hw = rc6->prev_hw_residency[i];
796-
rc6->prev_hw_residency[i] = time_hw;
793+
prev_hw = rc6->prev_hw_residency[id];
794+
rc6->prev_hw_residency[id] = time_hw;
797795

798796
/* RC6 delta from last sample. */
799797
if (time_hw >= prev_hw)
@@ -802,18 +800,31 @@ u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, const i915_reg_t reg)
802800
time_hw += overflow_hw - prev_hw;
803801

804802
/* Add delta to RC6 extended raw driver copy. */
805-
time_hw += rc6->cur_residency[i];
806-
rc6->cur_residency[i] = time_hw;
803+
time_hw += rc6->cur_residency[id];
804+
rc6->cur_residency[id] = time_hw;
807805

808806
intel_uncore_forcewake_put__locked(uncore, fw_domains);
809807
spin_unlock_irqrestore(&uncore->lock, flags);
810808

811809
return mul_u64_u32_div(time_hw, mul, div);
812810
}
813811

814-
u64 intel_rc6_residency_us(struct intel_rc6 *rc6, i915_reg_t reg)
812+
u64 intel_rc6_residency_us(struct intel_rc6 *rc6, enum intel_rc6_res_type id)
813+
{
814+
return DIV_ROUND_UP_ULL(intel_rc6_residency_ns(rc6, id), 1000);
815+
}
816+
817+
void intel_rc6_print_residency(struct seq_file *m, const char *title,
818+
enum intel_rc6_res_type id)
815819
{
816-
return DIV_ROUND_UP_ULL(intel_rc6_residency_ns(rc6, reg), 1000);
820+
struct intel_gt *gt = m->private;
821+
i915_reg_t reg = gt->rc6.res_reg[id];
822+
intel_wakeref_t wakeref;
823+
824+
with_intel_runtime_pm(gt->uncore->rpm, wakeref)
825+
seq_printf(m, "%s %u (%llu us)\n", title,
826+
intel_uncore_read(gt->uncore, reg),
827+
intel_rc6_residency_us(&gt->rc6, id));
817828
}
818829

819830
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)

‎drivers/gpu/drm/i915/gt/intel_rc6.h

Lines changed: 7 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -6,10 +6,11 @@
66
#ifndef INTEL_RC6_H
77
#define INTEL_RC6_H
88

9-
#include "i915_reg_defs.h"
9+
#include <linux/types.h>
1010

11-
struct intel_engine_cs;
11+
enum intel_rc6_res_type;
1212
struct intel_rc6;
13+
struct seq_file;
1314

1415
void intel_rc6_init(struct intel_rc6 *rc6);
1516
void intel_rc6_fini(struct intel_rc6 *rc6);
@@ -21,7 +22,9 @@ void intel_rc6_sanitize(struct intel_rc6 *rc6);
2122
void intel_rc6_enable(struct intel_rc6 *rc6);
2223
void intel_rc6_disable(struct intel_rc6 *rc6);
2324

24-
u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, i915_reg_t reg);
25-
u64 intel_rc6_residency_us(struct intel_rc6 *rc6, i915_reg_t reg);
25+
u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, enum intel_rc6_res_type id);
26+
u64 intel_rc6_residency_us(struct intel_rc6 *rc6, enum intel_rc6_res_type id);
27+
void intel_rc6_print_residency(struct seq_file *m, const char *title,
28+
enum intel_rc6_res_type id);
2629

2730
#endif /* INTEL_RC6_H */

‎drivers/gpu/drm/i915/gt/intel_rc6_types.h

Lines changed: 13 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -13,9 +13,20 @@
1313

1414
struct drm_i915_gem_object;
1515

16+
/* RC6 residency types */
17+
enum intel_rc6_res_type {
18+
INTEL_RC6_RES_RC6_LOCKED,
19+
INTEL_RC6_RES_RC6,
20+
INTEL_RC6_RES_RC6p,
21+
INTEL_RC6_RES_RC6pp,
22+
INTEL_RC6_RES_MAX,
23+
INTEL_RC6_RES_VLV_MEDIA = INTEL_RC6_RES_RC6p,
24+
};
25+
1626
struct intel_rc6 {
17-
u64 prev_hw_residency[4];
18-
u64 cur_residency[4];
27+
i915_reg_t res_reg[INTEL_RC6_RES_MAX];
28+
u64 prev_hw_residency[INTEL_RC6_RES_MAX];
29+
u64 cur_residency[INTEL_RC6_RES_MAX];
1930

2031
u32 ctl_enable;
2132

‎drivers/gpu/drm/i915/gt/selftest_rc6.c

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -19,11 +19,11 @@ static u64 rc6_residency(struct intel_rc6 *rc6)
1919

2020
/* XXX VLV_GT_MEDIA_RC6? */
2121

22-
result = intel_rc6_residency_ns(rc6, GEN6_GT_GFX_RC6);
22+
result = intel_rc6_residency_ns(rc6, INTEL_RC6_RES_RC6);
2323
if (HAS_RC6p(rc6_to_i915(rc6)))
24-
result += intel_rc6_residency_ns(rc6, GEN6_GT_GFX_RC6p);
24+
result += intel_rc6_residency_ns(rc6, INTEL_RC6_RES_RC6p);
2525
if (HAS_RC6pp(rc6_to_i915(rc6)))
26-
result += intel_rc6_residency_ns(rc6, GEN6_GT_GFX_RC6pp);
26+
result += intel_rc6_residency_ns(rc6, INTEL_RC6_RES_RC6pp);
2727

2828
return result;
2929
}

‎drivers/gpu/drm/i915/i915_pmu.c

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -148,13 +148,13 @@ static u64 __get_rc6(struct intel_gt *gt)
148148
struct drm_i915_private *i915 = gt->i915;
149149
u64 val;
150150

151-
val = intel_rc6_residency_ns(&gt->rc6, GEN6_GT_GFX_RC6);
151+
val = intel_rc6_residency_ns(&gt->rc6, INTEL_RC6_RES_RC6);
152152

153153
if (HAS_RC6p(i915))
154-
val += intel_rc6_residency_ns(&gt->rc6, GEN6_GT_GFX_RC6p);
154+
val += intel_rc6_residency_ns(&gt->rc6, INTEL_RC6_RES_RC6p);
155155

156156
if (HAS_RC6pp(i915))
157-
val += intel_rc6_residency_ns(&gt->rc6, GEN6_GT_GFX_RC6pp);
157+
val += intel_rc6_residency_ns(&gt->rc6, INTEL_RC6_RES_RC6pp);
158158

159159
return val;
160160
}

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