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bjorn-helgaasbjorn-helgaas
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Merge branch 'pci/controller/cadence'
- Add j721e DT and driver support for 'num-lanes' for devices that support x1, x2, or x4 Links (Matt Ranostay) - Add j721e DT compatible strings and driver support for j784s4 (Matt Ranostay) - Make TI J721E Kconfig depend on ARCH_K3 since the hardware is specific to those TI SoC parts (Peter Robinson) * pci/controller/cadence: PCI: j721e: Make TI J721E depend on ARCH_K3 PCI: j721e: Add TI J784S4 PCIe configuration PCI: j721e: Add PCIe 4x lane selection support PCI: j721e: Add per platform maximum lane settings dt-bindings: PCI: ti,j721e-pci-*: Add j784s4-pci-* compatible strings dt-bindings: PCI: ti,j721e-pci-*: Add checks for num-lanes
2 parents 6f77f0a + 177c9ac commit 78fe51f

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4 files changed

+114
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lines changed

‎Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml

Lines changed: 36 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -10,13 +10,11 @@ title: TI J721E PCI EP (PCIe Wrapper)
1010
maintainers:
1111
- Kishon Vijay Abraham I <[email protected]>
1212

13-
allOf:
14-
- $ref: cdns-pcie-ep.yaml#
15-
1613
properties:
1714
compatible:
1815
oneOf:
1916
- const: ti,j721e-pcie-ep
17+
- const: ti,j784s4-pcie-ep
2018
- description: PCIe EP controller in AM64
2119
items:
2220
- const: ti,am64-pcie-ep
@@ -65,6 +63,41 @@ properties:
6563
items:
6664
- const: link_state
6765

66+
allOf:
67+
- $ref: cdns-pcie-ep.yaml#
68+
- if:
69+
properties:
70+
compatible:
71+
enum:
72+
- ti,am64-pcie-ep
73+
then:
74+
properties:
75+
num-lanes:
76+
const: 1
77+
78+
- if:
79+
properties:
80+
compatible:
81+
enum:
82+
- ti,j7200-pcie-ep
83+
- ti,j721e-pcie-ep
84+
then:
85+
properties:
86+
num-lanes:
87+
minimum: 1
88+
maximum: 2
89+
90+
- if:
91+
properties:
92+
compatible:
93+
enum:
94+
- ti,j784s4-pcie-ep
95+
then:
96+
properties:
97+
num-lanes:
98+
minimum: 1
99+
maximum: 4
100+
68101
required:
69102
- compatible
70103
- reg

‎Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml

Lines changed: 36 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -10,13 +10,11 @@ title: TI J721E PCI Host (PCIe Wrapper)
1010
maintainers:
1111
- Kishon Vijay Abraham I <[email protected]>
1212

13-
allOf:
14-
- $ref: cdns-pcie-host.yaml#
15-
1613
properties:
1714
compatible:
1815
oneOf:
1916
- const: ti,j721e-pcie-host
17+
- const: ti,j784s4-pcie-host
2018
- description: PCIe controller in AM64
2119
items:
2220
- const: ti,am64-pcie-host
@@ -94,6 +92,41 @@ properties:
9492
interrupts:
9593
maxItems: 1
9694

95+
allOf:
96+
- $ref: cdns-pcie-host.yaml#
97+
- if:
98+
properties:
99+
compatible:
100+
enum:
101+
- ti,am64-pcie-host
102+
then:
103+
properties:
104+
num-lanes:
105+
const: 1
106+
107+
- if:
108+
properties:
109+
compatible:
110+
enum:
111+
- ti,j7200-pcie-host
112+
- ti,j721e-pcie-host
113+
then:
114+
properties:
115+
num-lanes:
116+
minimum: 1
117+
maximum: 2
118+
119+
- if:
120+
properties:
121+
compatible:
122+
enum:
123+
- ti,j784s4-pcie-host
124+
then:
125+
properties:
126+
num-lanes:
127+
minimum: 1
128+
maximum: 4
129+
97130
required:
98131
- compatible
99132
- reg

‎drivers/pci/controller/cadence/Kconfig

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -47,6 +47,7 @@ config PCI_J721E
4747

4848
config PCI_J721E_HOST
4949
bool "TI J721E PCIe controller (host mode)"
50+
depends on ARCH_K3 || COMPILE_TEST
5051
depends on OF
5152
select PCIE_CADENCE_HOST
5253
select PCI_J721E
@@ -57,6 +58,7 @@ config PCI_J721E_HOST
5758

5859
config PCI_J721E_EP
5960
bool "TI J721E PCIe controller (endpoint mode)"
61+
depends on ARCH_K3 || COMPILE_TEST
6062
depends on OF
6163
depends on PCI_ENDPOINT
6264
select PCIE_CADENCE_EP

‎drivers/pci/controller/cadence/pci-j721e.c

Lines changed: 40 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -42,18 +42,16 @@ enum link_status {
4242
};
4343

4444
#define J721E_MODE_RC BIT(7)
45-
#define LANE_COUNT_MASK BIT(8)
4645
#define LANE_COUNT(n) ((n) << 8)
4746

4847
#define GENERATION_SEL_MASK GENMASK(1, 0)
4948

50-
#define MAX_LANES 2
51-
5249
struct j721e_pcie {
5350
struct cdns_pcie *cdns_pcie;
5451
struct clk *refclk;
5552
u32 mode;
5653
u32 num_lanes;
54+
u32 max_lanes;
5755
void __iomem *user_cfg_base;
5856
void __iomem *intd_cfg_base;
5957
u32 linkdown_irq_regfield;
@@ -71,6 +69,7 @@ struct j721e_pcie_data {
7169
unsigned int quirk_disable_flr:1;
7270
u32 linkdown_irq_regfield;
7371
unsigned int byte_access_allowed:1;
72+
unsigned int max_lanes;
7473
};
7574

7675
static inline u32 j721e_pcie_user_readl(struct j721e_pcie *pcie, u32 offset)
@@ -206,11 +205,15 @@ static int j721e_pcie_set_lane_count(struct j721e_pcie *pcie,
206205
{
207206
struct device *dev = pcie->cdns_pcie->dev;
208207
u32 lanes = pcie->num_lanes;
208+
u32 mask = BIT(8);
209209
u32 val = 0;
210210
int ret;
211211

212+
if (pcie->max_lanes == 4)
213+
mask = GENMASK(9, 8);
214+
212215
val = LANE_COUNT(lanes - 1);
213-
ret = regmap_update_bits(syscon, offset, LANE_COUNT_MASK, val);
216+
ret = regmap_update_bits(syscon, offset, mask, val);
214217
if (ret)
215218
dev_err(dev, "failed to set link count\n");
216219

@@ -290,35 +293,55 @@ static const struct j721e_pcie_data j721e_pcie_rc_data = {
290293
.quirk_retrain_flag = true,
291294
.byte_access_allowed = false,
292295
.linkdown_irq_regfield = LINK_DOWN,
296+
.max_lanes = 2,
293297
};
294298

295299
static const struct j721e_pcie_data j721e_pcie_ep_data = {
296300
.mode = PCI_MODE_EP,
297301
.linkdown_irq_regfield = LINK_DOWN,
302+
.max_lanes = 2,
298303
};
299304

300305
static const struct j721e_pcie_data j7200_pcie_rc_data = {
301306
.mode = PCI_MODE_RC,
302307
.quirk_detect_quiet_flag = true,
303308
.linkdown_irq_regfield = J7200_LINK_DOWN,
304309
.byte_access_allowed = true,
310+
.max_lanes = 2,
305311
};
306312

307313
static const struct j721e_pcie_data j7200_pcie_ep_data = {
308314
.mode = PCI_MODE_EP,
309315
.quirk_detect_quiet_flag = true,
310316
.quirk_disable_flr = true,
317+
.max_lanes = 2,
311318
};
312319

313320
static const struct j721e_pcie_data am64_pcie_rc_data = {
314321
.mode = PCI_MODE_RC,
315322
.linkdown_irq_regfield = J7200_LINK_DOWN,
316323
.byte_access_allowed = true,
324+
.max_lanes = 1,
317325
};
318326

319327
static const struct j721e_pcie_data am64_pcie_ep_data = {
320328
.mode = PCI_MODE_EP,
321329
.linkdown_irq_regfield = J7200_LINK_DOWN,
330+
.max_lanes = 1,
331+
};
332+
333+
static const struct j721e_pcie_data j784s4_pcie_rc_data = {
334+
.mode = PCI_MODE_RC,
335+
.quirk_retrain_flag = true,
336+
.byte_access_allowed = false,
337+
.linkdown_irq_regfield = LINK_DOWN,
338+
.max_lanes = 4,
339+
};
340+
341+
static const struct j721e_pcie_data j784s4_pcie_ep_data = {
342+
.mode = PCI_MODE_EP,
343+
.linkdown_irq_regfield = LINK_DOWN,
344+
.max_lanes = 4,
322345
};
323346

324347
static const struct of_device_id of_j721e_pcie_match[] = {
@@ -346,6 +369,14 @@ static const struct of_device_id of_j721e_pcie_match[] = {
346369
.compatible = "ti,am64-pcie-ep",
347370
.data = &am64_pcie_ep_data,
348371
},
372+
{
373+
.compatible = "ti,j784s4-pcie-host",
374+
.data = &j784s4_pcie_rc_data,
375+
},
376+
{
377+
.compatible = "ti,j784s4-pcie-ep",
378+
.data = &j784s4_pcie_ep_data,
379+
},
349380
{},
350381
};
351382

@@ -432,9 +463,13 @@ static int j721e_pcie_probe(struct platform_device *pdev)
432463
pcie->user_cfg_base = base;
433464

434465
ret = of_property_read_u32(node, "num-lanes", &num_lanes);
435-
if (ret || num_lanes > MAX_LANES)
466+
if (ret || num_lanes > data->max_lanes) {
467+
dev_warn(dev, "num-lanes property not provided or invalid, setting num-lanes to 1\n");
436468
num_lanes = 1;
469+
}
470+
437471
pcie->num_lanes = num_lanes;
472+
pcie->max_lanes = data->max_lanes;
438473

439474
if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48)))
440475
return -EINVAL;

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