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shramamoorthylag-linaro
shramamoorthy
authored and
lag-linaro
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mfd: tps65219: Add support for TI TPS65214 PMIC
Use chip ID and chip_data struct to differentiate between 3 PMIC devices in probe(). Add TPS65214 resource information. Update descriptions and copyright information to reflect the driver supports 3 PMIC devices. Signed-off-by: Shree Ramamoorthy <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Lee Jones <[email protected]>
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‎drivers/mfd/tps65219.c

Lines changed: 124 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
// SPDX-License-Identifier: GPL-2.0
22
//
3-
// Driver for TPS65215/TPS65219 Power Management Integrated Chips (PMIC)
3+
// Driver for TPS65214/TPS65215/TPS65219 Power Management Integrated Chips
44
//
55
// Copyright (C) 2022 BayLibre Incorporated - https://www.baylibre.com/
66
// Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
@@ -60,6 +60,44 @@ static const struct resource tps65219_pwrbutton_resources[] = {
6060
DEFINE_RES_IRQ_NAMED(TPS65219_INT_PB_RISING_EDGE_DETECT, "rising"),
6161
};
6262

63+
static const struct resource tps65214_regulator_resources[] = {
64+
DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO1_SCG, "LDO1_SCG"),
65+
DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO1_OC, "LDO1_OC"),
66+
DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO1_UV, "LDO1_UV"),
67+
DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO2_SCG, "LDO2_SCG"),
68+
DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO2_OC, "LDO2_OC"),
69+
DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO2_UV, "LDO2_UV"),
70+
DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK3_SCG, "BUCK3_SCG"),
71+
DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK3_OC, "BUCK3_OC"),
72+
DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK3_NEG_OC, "BUCK3_NEG_OC"),
73+
DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK3_UV, "BUCK3_UV"),
74+
DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK1_SCG, "BUCK1_SCG"),
75+
DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK1_OC, "BUCK1_OC"),
76+
DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK1_NEG_OC, "BUCK1_NEG_OC"),
77+
DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK1_UV, "BUCK1_UV"),
78+
DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK2_SCG, "BUCK2_SCG"),
79+
DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK2_OC, "BUCK2_OC"),
80+
DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK2_NEG_OC, "BUCK2_NEG_OC"),
81+
DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK2_UV, "BUCK2_UV"),
82+
DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK1_RV, "BUCK1_RV"),
83+
DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK2_RV, "BUCK2_RV"),
84+
DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK3_RV, "BUCK3_RV"),
85+
DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO1_RV, "LDO1_RV"),
86+
DEFINE_RES_IRQ_NAMED(TPS65214_INT_LDO2_RV, "LDO2_RV"),
87+
DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK1_RV_SD, "BUCK1_RV_SD"),
88+
DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK2_RV_SD, "BUCK2_RV_SD"),
89+
DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK3_RV_SD, "BUCK3_RV_SD"),
90+
DEFINE_RES_IRQ_NAMED(TPS65214_INT_LDO1_RV_SD, "LDO1_RV_SD"),
91+
DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO2_RV_SD, "LDO2_RV_SD"),
92+
DEFINE_RES_IRQ_NAMED(TPS65219_INT_TIMEOUT, "TIMEOUT"),
93+
DEFINE_RES_IRQ_NAMED(TPS65219_INT_SENSOR_2_WARM, "SENSOR_2_WARM"),
94+
DEFINE_RES_IRQ_NAMED(TPS65219_INT_SENSOR_1_WARM, "SENSOR_1_WARM"),
95+
DEFINE_RES_IRQ_NAMED(TPS65219_INT_SENSOR_0_WARM, "SENSOR_0_WARM"),
96+
DEFINE_RES_IRQ_NAMED(TPS65219_INT_SENSOR_2_HOT, "SENSOR_2_HOT"),
97+
DEFINE_RES_IRQ_NAMED(TPS65219_INT_SENSOR_1_HOT, "SENSOR_1_HOT"),
98+
DEFINE_RES_IRQ_NAMED(TPS65219_INT_SENSOR_0_HOT, "SENSOR_0_HOT"),
99+
};
100+
63101
static const struct resource tps65215_regulator_resources[] = {
64102
DEFINE_RES_IRQ_NAMED(TPS65215_INT_LDO1_SCG, "LDO1_SCG"),
65103
DEFINE_RES_IRQ_NAMED(TPS65215_INT_LDO1_OC, "LDO1_OC"),
@@ -150,6 +188,11 @@ static const struct resource tps65219_regulator_resources[] = {
150188
DEFINE_RES_IRQ_NAMED(TPS65219_INT_SENSOR_0_HOT, "SENSOR_0_HOT"),
151189
};
152190

191+
static const struct mfd_cell tps65214_cells[] = {
192+
MFD_CELL_RES("tps65214-regulator", tps65214_regulator_resources),
193+
MFD_CELL_NAME("tps65215-gpio"),
194+
};
195+
153196
static const struct mfd_cell tps65215_cells[] = {
154197
MFD_CELL_RES("tps65215-regulator", tps65215_regulator_resources),
155198
MFD_CELL_NAME("tps65215-gpio"),
@@ -186,6 +229,15 @@ static unsigned int tps65215_bit5_offsets[] = { TPS65215_REG_INT_LDO_1_POS };
186229
static unsigned int tps65215_bit6_offsets[] = { TPS65215_REG_INT_LDO_2_POS };
187230
static unsigned int bit7_offsets[] = { TPS65219_REG_INT_PB_POS }; /* Power Button */
188231

232+
/* TPS65214 INT_SOURCE bit 6 is 'RESERVED'*/
233+
static unsigned int tps65214_bit0_offsets[] = { TPS65214_REG_INT_TO_RV_POS };
234+
static unsigned int tps65214_bit1_offsets[] = { TPS65214_REG_INT_RV_POS };
235+
static unsigned int tps65214_bit2_offsets[] = { TPS65214_REG_INT_SYS_POS };
236+
static unsigned int tps65214_bit3_offsets[] = { TPS65214_REG_INT_BUCK_1_2_POS };
237+
static unsigned int tps65214_bit4_offsets[] = { TPS65214_REG_INT_BUCK_3_POS };
238+
static unsigned int tps65214_bit5_offsets[] = { TPS65214_REG_INT_LDO_1_2_POS };
239+
static unsigned int tps65214_bit7_offsets[] = { TPS65214_REG_INT_PB_POS };
240+
189241
static struct regmap_irq_sub_irq_map tps65219_sub_irq_offsets[] = {
190242
REGMAP_IRQ_MAIN_REG_OFFSET(bit0_offsets),
191243
REGMAP_IRQ_MAIN_REG_OFFSET(bit1_offsets),
@@ -208,9 +260,59 @@ static struct regmap_irq_sub_irq_map tps65215_sub_irq_offsets[] = {
208260
REGMAP_IRQ_MAIN_REG_OFFSET(bit7_offsets),
209261
};
210262

263+
static struct regmap_irq_sub_irq_map tps65214_sub_irq_offsets[] = {
264+
REGMAP_IRQ_MAIN_REG_OFFSET(tps65214_bit0_offsets),
265+
REGMAP_IRQ_MAIN_REG_OFFSET(tps65214_bit1_offsets),
266+
REGMAP_IRQ_MAIN_REG_OFFSET(tps65214_bit2_offsets),
267+
REGMAP_IRQ_MAIN_REG_OFFSET(tps65214_bit3_offsets),
268+
REGMAP_IRQ_MAIN_REG_OFFSET(tps65214_bit4_offsets),
269+
REGMAP_IRQ_MAIN_REG_OFFSET(tps65214_bit5_offsets),
270+
REGMAP_IRQ_MAIN_REG_OFFSET(tps65214_bit7_offsets),
271+
};
272+
211273
#define TPS65219_REGMAP_IRQ_REG(int_name, register_position) \
212274
REGMAP_IRQ_REG(int_name, register_position, int_name##_MASK)
213275

276+
static const struct regmap_irq tps65214_irqs[] = {
277+
TPS65219_REGMAP_IRQ_REG(TPS65219_INT_LDO1_SCG, TPS65214_REG_INT_LDO_1_2_POS),
278+
TPS65219_REGMAP_IRQ_REG(TPS65219_INT_LDO1_OC, TPS65214_REG_INT_LDO_1_2_POS),
279+
TPS65219_REGMAP_IRQ_REG(TPS65219_INT_LDO1_UV, TPS65214_REG_INT_LDO_1_2_POS),
280+
TPS65219_REGMAP_IRQ_REG(TPS65219_INT_LDO2_SCG, TPS65214_REG_INT_LDO_1_2_POS),
281+
TPS65219_REGMAP_IRQ_REG(TPS65219_INT_LDO2_OC, TPS65214_REG_INT_LDO_1_2_POS),
282+
TPS65219_REGMAP_IRQ_REG(TPS65219_INT_LDO2_UV, TPS65214_REG_INT_LDO_1_2_POS),
283+
TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK3_SCG, TPS65214_REG_INT_BUCK_3_POS),
284+
TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK3_OC, TPS65214_REG_INT_BUCK_3_POS),
285+
TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK3_NEG_OC, TPS65214_REG_INT_BUCK_3_POS),
286+
TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK3_UV, TPS65214_REG_INT_BUCK_3_POS),
287+
TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK2_SCG, TPS65214_REG_INT_BUCK_1_2_POS),
288+
TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK2_OC, TPS65214_REG_INT_BUCK_1_2_POS),
289+
TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK2_NEG_OC, TPS65214_REG_INT_BUCK_1_2_POS),
290+
TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK2_UV, TPS65214_REG_INT_BUCK_1_2_POS),
291+
TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK1_SCG, TPS65214_REG_INT_BUCK_1_2_POS),
292+
TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK1_OC, TPS65214_REG_INT_BUCK_1_2_POS),
293+
TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK1_NEG_OC, TPS65214_REG_INT_BUCK_1_2_POS),
294+
TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK1_UV, TPS65214_REG_INT_BUCK_1_2_POS),
295+
TPS65219_REGMAP_IRQ_REG(TPS65219_INT_SENSOR_2_WARM, TPS65214_REG_INT_SYS_POS),
296+
TPS65219_REGMAP_IRQ_REG(TPS65219_INT_SENSOR_1_WARM, TPS65214_REG_INT_SYS_POS),
297+
TPS65219_REGMAP_IRQ_REG(TPS65219_INT_SENSOR_0_WARM, TPS65214_REG_INT_SYS_POS),
298+
TPS65219_REGMAP_IRQ_REG(TPS65219_INT_SENSOR_2_HOT, TPS65214_REG_INT_SYS_POS),
299+
TPS65219_REGMAP_IRQ_REG(TPS65219_INT_SENSOR_1_HOT, TPS65214_REG_INT_SYS_POS),
300+
TPS65219_REGMAP_IRQ_REG(TPS65219_INT_SENSOR_0_HOT, TPS65214_REG_INT_SYS_POS),
301+
TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK1_RV, TPS65214_REG_INT_RV_POS),
302+
TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK2_RV, TPS65214_REG_INT_RV_POS),
303+
TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK3_RV, TPS65214_REG_INT_RV_POS),
304+
TPS65219_REGMAP_IRQ_REG(TPS65219_INT_LDO1_RV, TPS65214_REG_INT_RV_POS),
305+
TPS65219_REGMAP_IRQ_REG(TPS65214_INT_LDO2_RV, TPS65214_REG_INT_RV_POS),
306+
TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK1_RV_SD, TPS65214_REG_INT_TO_RV_POS),
307+
TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK2_RV_SD, TPS65214_REG_INT_TO_RV_POS),
308+
TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK3_RV_SD, TPS65214_REG_INT_TO_RV_POS),
309+
TPS65219_REGMAP_IRQ_REG(TPS65214_INT_LDO1_RV_SD, TPS65214_REG_INT_TO_RV_POS),
310+
TPS65219_REGMAP_IRQ_REG(TPS65219_INT_LDO2_RV_SD, TPS65214_REG_INT_TO_RV_POS),
311+
TPS65219_REGMAP_IRQ_REG(TPS65219_INT_TIMEOUT, TPS65214_REG_INT_TO_RV_POS),
312+
TPS65219_REGMAP_IRQ_REG(TPS65219_INT_PB_FALLING_EDGE_DETECT, TPS65214_REG_INT_PB_POS),
313+
TPS65219_REGMAP_IRQ_REG(TPS65219_INT_PB_RISING_EDGE_DETECT, TPS65214_REG_INT_PB_POS),
314+
};
315+
214316
static const struct regmap_irq tps65215_irqs[] = {
215317
TPS65219_REGMAP_IRQ_REG(TPS65215_INT_LDO1_SCG, TPS65215_REG_INT_LDO_1_POS),
216318
TPS65219_REGMAP_IRQ_REG(TPS65215_INT_LDO1_OC, TPS65215_REG_INT_LDO_1_POS),
@@ -305,6 +407,20 @@ static const struct regmap_irq tps65219_irqs[] = {
305407
TPS65219_REGMAP_IRQ_REG(TPS65219_INT_PB_RISING_EDGE_DETECT, TPS65219_REG_INT_PB_POS),
306408
};
307409

410+
static const struct regmap_irq_chip tps65214_irq_chip = {
411+
.name = "tps65214_irq",
412+
.main_status = TPS65219_REG_INT_SOURCE,
413+
.num_main_regs = 1,
414+
.num_main_status_bits = 8,
415+
.irqs = tps65214_irqs,
416+
.num_irqs = ARRAY_SIZE(tps65214_irqs),
417+
.status_base = TPS65214_REG_INT_LDO_1_2,
418+
.ack_base = TPS65214_REG_INT_LDO_1_2,
419+
.clear_ack = 1,
420+
.num_regs = 8,
421+
.sub_reg_offsets = tps65214_sub_irq_offsets,
422+
};
423+
308424
static const struct regmap_irq_chip tps65215_irq_chip = {
309425
.name = "tps65215_irq",
310426
.main_status = TPS65219_REG_INT_SOURCE,
@@ -340,6 +456,11 @@ struct tps65219_chip_data {
340456
};
341457

342458
static struct tps65219_chip_data chip_info_table[] = {
459+
[TPS65214] = {
460+
.irq_chip = &tps65214_irq_chip,
461+
.cells = tps65214_cells,
462+
.n_cells = ARRAY_SIZE(tps65214_cells),
463+
},
343464
[TPS65215] = {
344465
.irq_chip = &tps65215_irq_chip,
345466
.cells = tps65215_cells,
@@ -421,6 +542,7 @@ static int tps65219_probe(struct i2c_client *client)
421542
}
422543

423544
static const struct of_device_id of_tps65219_match_table[] = {
545+
{ .compatible = "ti,tps65214", .data = (void *)TPS65214, },
424546
{ .compatible = "ti,tps65215", .data = (void *)TPS65215, },
425547
{ .compatible = "ti,tps65219", .data = (void *)TPS65219, },
426548
{}
@@ -437,5 +559,5 @@ static struct i2c_driver tps65219_driver = {
437559
module_i2c_driver(tps65219_driver);
438560

439561
MODULE_AUTHOR("Jerome Neanne <[email protected]>");
440-
MODULE_DESCRIPTION("TPS65215/TPS65219 PMIC driver");
562+
MODULE_DESCRIPTION("TPS65214/TPS65215/TPS65219 PMIC driver");
441563
MODULE_LICENSE("GPL");

‎include/linux/mfd/tps65219.h

Lines changed: 60 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -16,6 +16,7 @@
1616

1717
/* Chip id list*/
1818
enum pmic_id {
19+
TPS65214,
1920
TPS65215,
2021
TPS65219,
2122
};
@@ -28,17 +29,23 @@ enum pmic_id {
2829
#define TPS65219_REG_NVM_ID 0x01
2930
#define TPS65219_REG_ENABLE_CTRL 0x02
3031
#define TPS65219_REG_BUCKS_CONFIG 0x03
32+
#define TPS65214_REG_LOCK 0x03
3133
#define TPS65219_REG_LDO4_VOUT 0x04
34+
#define TPS65214_REG_LDO1_VOUT_STBY 0x04
3235
#define TPS65219_REG_LDO3_VOUT 0x05
3336
#define TPS65215_REG_LDO2_VOUT 0x05
37+
#define TPS65214_REG_LDO1_VOUT 0x05
3438
#define TPS65219_REG_LDO2_VOUT 0x06
39+
#define TPS65214_REG_LDO2_VOUT 0x06
3540
#define TPS65219_REG_LDO1_VOUT 0x07
41+
#define TPS65214_REG_LDO2_VOUT_STBY 0x07
3642
#define TPS65219_REG_BUCK3_VOUT 0x8
3743
#define TPS65219_REG_BUCK2_VOUT 0x9
3844
#define TPS65219_REG_BUCK1_VOUT 0xA
3945
#define TPS65219_REG_LDO4_SEQUENCE_SLOT 0xB
4046
#define TPS65219_REG_LDO3_SEQUENCE_SLOT 0xC
4147
#define TPS65215_REG_LDO2_SEQUENCE_SLOT 0xC
48+
#define TPS65214_REG_LDO1_SEQUENCE_SLOT 0xC
4249
#define TPS65219_REG_LDO2_SEQUENCE_SLOT 0xD
4350
#define TPS65219_REG_LDO1_SEQUENCE_SLOT 0xE
4451
#define TPS65219_REG_BUCK3_SEQUENCE_SLOT 0xF
@@ -47,15 +54,21 @@ enum pmic_id {
4754
#define TPS65219_REG_nRST_SEQUENCE_SLOT 0x12
4855
#define TPS65219_REG_GPIO_SEQUENCE_SLOT 0x13
4956
#define TPS65219_REG_GPO2_SEQUENCE_SLOT 0x14
57+
#define TPS65214_REG_GPIO_GPI_SEQUENCE_SLOT 0x14
5058
#define TPS65219_REG_GPO1_SEQUENCE_SLOT 0x15
59+
#define TPS65214_REG_GPO_SEQUENCE_SLOT 0x15
5160
#define TPS65219_REG_POWER_UP_SLOT_DURATION_1 0x16
5261
#define TPS65219_REG_POWER_UP_SLOT_DURATION_2 0x17
62+
/* _SLOT_DURATION_3 doesn't apply to TPS65215*/
5363
#define TPS65219_REG_POWER_UP_SLOT_DURATION_3 0x18
5464
#define TPS65219_REG_POWER_UP_SLOT_DURATION_4 0x19
65+
#define TPS65214_REG_BUCK3_VOUT_STBY 0x19
5566
#define TPS65219_REG_POWER_DOWN_SLOT_DURATION_1 0x1A
5667
#define TPS65219_REG_POWER_DOWN_SLOT_DURATION_2 0x1B
5768
#define TPS65219_REG_POWER_DOWN_SLOT_DURATION_3 0x1C
69+
#define TPS65214_REG_BUCK2_VOUT_STBY 0x1C
5870
#define TPS65219_REG_POWER_DOWN_SLOT_DURATION_4 0x1D
71+
#define TPS65214_REG_BUCK1_VOUT_STBY 0x1D
5972
#define TPS65219_REG_GENERAL_CONFIG 0x1E
6073
#define TPS65219_REG_MFP_1_CONFIG 0x1F
6174
#define TPS65219_REG_MFP_2_CONFIG 0x20
@@ -82,6 +95,9 @@ enum pmic_id {
8295
#define TPS65215_REG_INT_LDO_2 0x2C
8396
#define TPS65215_REG_INT_LDO_1 0x2D
8497

98+
/* TPS65214 specific 'sub irq' register */
99+
#define TPS65214_REG_INT_LDO_1_2 0x2D
100+
85101
/* Common TPS65215 & TPS65219 'sub irq' registers */
86102
#define TPS65219_REG_INT_BUCK_3 0x2E
87103
#define TPS65219_REG_INT_BUCK_1_2 0x2F
@@ -102,6 +118,14 @@ enum pmic_id {
102118
#define TPS65215_REG_INT_LDO_2_POS 0
103119
#define TPS65215_REG_INT_LDO_1_POS 1
104120

121+
#define TPS65214_REG_INT_LDO_1_2_POS 0
122+
#define TPS65214_REG_INT_BUCK_3_POS 1
123+
#define TPS65214_REG_INT_BUCK_1_2_POS 2
124+
#define TPS65214_REG_INT_SYS_POS 3
125+
#define TPS65214_REG_INT_RV_POS 4
126+
#define TPS65214_REG_INT_TO_RV_POS 5
127+
#define TPS65214_REG_INT_PB_POS 6
128+
105129
#define TPS65219_REG_USER_NVM_CMD 0x34
106130
#define TPS65219_REG_POWER_UP_STATUS 0x35
107131
#define TPS65219_REG_SPARE_2 0x36
@@ -124,6 +148,7 @@ enum pmic_id {
124148
#define TPS65219_ENABLE_LDO2_EN_MASK BIT(4)
125149
#define TPS65219_ENABLE_LDO3_EN_MASK BIT(5)
126150
#define TPS65215_ENABLE_LDO2_EN_MASK BIT(5)
151+
#define TPS65214_ENABLE_LDO1_EN_MASK BIT(5)
127152
#define TPS65219_ENABLE_LDO4_EN_MASK BIT(6)
128153
/* power ON-OFF sequence slot */
129154
#define TPS65219_BUCKS_LDOS_SEQUENCE_OFF_SLOT_MASK GENMASK(3, 0)
@@ -175,14 +200,14 @@ enum pmic_id {
175200
#define TPS65219_REG_MASK_EFFECT_MASK GENMASK(2, 1)
176201
#define TPS65219_REG_MASK_INT_FOR_PB_MASK BIT(7)
177202
/* UnderVoltage - Short to GND - OverCurrent*/
178-
/* LDO3-4 */
203+
/* LDO3-4: only for TPS65219*/
179204
#define TPS65219_INT_LDO3_SCG_MASK BIT(0)
180205
#define TPS65219_INT_LDO3_OC_MASK BIT(1)
181206
#define TPS65219_INT_LDO3_UV_MASK BIT(2)
182207
#define TPS65219_INT_LDO4_SCG_MASK BIT(3)
183208
#define TPS65219_INT_LDO4_OC_MASK BIT(4)
184209
#define TPS65219_INT_LDO4_UV_MASK BIT(5)
185-
/* LDO1-2 */
210+
/* LDO1-2: TPS65214 & TPS65219 */
186211
#define TPS65219_INT_LDO1_SCG_MASK BIT(0)
187212
#define TPS65219_INT_LDO1_OC_MASK BIT(1)
188213
#define TPS65219_INT_LDO1_UV_MASK BIT(2)
@@ -210,12 +235,13 @@ enum pmic_id {
210235
#define TPS65219_INT_BUCK2_OC_MASK BIT(5)
211236
#define TPS65219_INT_BUCK2_NEG_OC_MASK BIT(6)
212237
#define TPS65219_INT_BUCK2_UV_MASK BIT(7)
213-
/* Thermal Sensor */
238+
/* Thermal Sensor: TPS65219/TPS65215 */
214239
#define TPS65219_INT_SENSOR_3_WARM_MASK BIT(0)
240+
#define TPS65219_INT_SENSOR_3_HOT_MASK BIT(4)
241+
/* Thermal Sensor: TPS65219/TPS65215/TPS65214 */
215242
#define TPS65219_INT_SENSOR_2_WARM_MASK BIT(1)
216243
#define TPS65219_INT_SENSOR_1_WARM_MASK BIT(2)
217244
#define TPS65219_INT_SENSOR_0_WARM_MASK BIT(3)
218-
#define TPS65219_INT_SENSOR_3_HOT_MASK BIT(4)
219245
#define TPS65219_INT_SENSOR_2_HOT_MASK BIT(5)
220246
#define TPS65219_INT_SENSOR_1_HOT_MASK BIT(6)
221247
#define TPS65219_INT_SENSOR_0_HOT_MASK BIT(7)
@@ -227,6 +253,7 @@ enum pmic_id {
227253
#define TPS65219_INT_LDO2_RV_MASK BIT(4)
228254
#define TPS65219_INT_LDO3_RV_MASK BIT(5)
229255
#define TPS65215_INT_LDO2_RV_MASK BIT(5)
256+
#define TPS65214_INT_LDO2_RV_MASK BIT(5)
230257
#define TPS65219_INT_LDO4_RV_MASK BIT(6)
231258
/* Residual Voltage ShutDown */
232259
#define TPS65219_INT_BUCK1_RV_SD_MASK BIT(0)
@@ -236,6 +263,7 @@ enum pmic_id {
236263
#define TPS65219_INT_LDO2_RV_SD_MASK BIT(4)
237264
#define TPS65219_INT_LDO3_RV_SD_MASK BIT(5)
238265
#define TPS65215_INT_LDO2_RV_SD_MASK BIT(5)
266+
#define TPS65214_INT_LDO1_RV_SD_MASK BIT(5)
239267
#define TPS65219_INT_LDO4_RV_SD_MASK BIT(6)
240268
#define TPS65219_INT_TIMEOUT_MASK BIT(7)
241269
/* Power Button */
@@ -269,7 +297,7 @@ enum {
269297
TPS65215_INT_LDO2_SCG,
270298
TPS65215_INT_LDO2_OC,
271299
TPS65215_INT_LDO2_UV,
272-
/* LDO1-2 */
300+
/* LDO1-2: TPS65219/TPS65214 */
273301
TPS65219_INT_LDO1_SCG,
274302
TPS65219_INT_LDO1_OC,
275303
TPS65219_INT_LDO1_UV,
@@ -306,13 +334,15 @@ enum {
306334
TPS65219_INT_LDO1_RV,
307335
TPS65219_INT_LDO2_RV,
308336
TPS65215_INT_LDO2_RV,
337+
TPS65214_INT_LDO2_RV,
309338
TPS65219_INT_LDO3_RV,
310339
TPS65219_INT_LDO4_RV,
311340
/* Residual Voltage ShutDown */
312341
TPS65219_INT_BUCK1_RV_SD,
313342
TPS65219_INT_BUCK2_RV_SD,
314343
TPS65219_INT_BUCK3_RV_SD,
315344
TPS65219_INT_LDO1_RV_SD,
345+
TPS65214_INT_LDO1_RV_SD,
316346
TPS65215_INT_LDO2_RV_SD,
317347
TPS65219_INT_LDO2_RV_SD,
318348
TPS65219_INT_LDO3_RV_SD,
@@ -323,6 +353,17 @@ enum {
323353
TPS65219_INT_PB_RISING_EDGE_DETECT,
324354
};
325355

356+
enum tps65214_regulator_id {
357+
/*
358+
* DCDC's same as TPS65219
359+
* LDO1 maps to TPS65219's LDO3
360+
* LDO2 is the same as TPS65219
361+
*
362+
*/
363+
TPS65214_LDO_1 = 3,
364+
TPS65214_LDO_2 = 4,
365+
};
366+
326367
enum tps65215_regulator_id {
327368
/* DCDC's same as TPS65219 */
328369
/* LDO1 is the same as TPS65219 */
@@ -346,9 +387,23 @@ enum tps65219_regulator_id {
346387
/* Number of LDO voltage regulators available */
347388
#define TPS65219_NUM_LDO 4
348389
#define TPS65215_NUM_LDO 2
390+
#define TPS65214_NUM_LDO 2
349391
/* Number of total regulators available */
350392
#define TPS65219_NUM_REGULATOR (TPS6521X_NUM_BUCKS + TPS65219_NUM_LDO)
351393
#define TPS65215_NUM_REGULATOR (TPS6521X_NUM_BUCKS + TPS65215_NUM_LDO)
394+
#define TPS65214_NUM_REGULATOR (TPS6521X_NUM_BUCKS + TPS65214_NUM_LDO)
395+
396+
/* Define the TPS65214 IRQ numbers */
397+
enum tps65214_irqs {
398+
/* INT source registers */
399+
TPS65214_TO_RV_SD_SET_IRQ,
400+
TPS65214_RV_SET_IRQ,
401+
TPS65214_SYS_SET_IRQ,
402+
TPS65214_BUCK_1_2_SET_IRQ,
403+
TPS65214_BUCK_3_SET_IRQ,
404+
TPS65214_LDO_1_2_SET_IRQ,
405+
TPS65214_PB_SET_IRQ = 7,
406+
};
352407

353408
/* Define the TPS65215 IRQ numbers */
354409
enum tps65215_irqs {

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