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Merge tag 'drm-fixes-2024-08-24' of https://gitlab.freedesktop.org/drm/kernel
Pull drm fixes from Dave Airlie: "Weekly fixes. xe and msm are the major groups, with amdgpu/i915/nouveau having smaller bits. xe has a bunch of hw workaround fixes that were found to be missing, so that is why there are a bunch of scattered fixes, and one larger one. But overall size doesn't look too out of the ordinary. msm: - virtual plane fixes: - drop yuv on hw where not supported - csc vs yuv format fix - rotation fix - fix fb cleanup on close - reset phy before link training - fix visual corruption at 4K - fix NULL ptr crash on hotplug - simplify debug macros - sc7180 fix - adreno firmware name error path fix amdgpu: - GFX10 firmware loading fix - SDMA 5.2 fix - Debugfs parameter validation fix - eGPU hotplug fix i915: - fix HDCP timeouts nouveau: - fix SG_DEBUG crash xe: - Fix OA format masks which were breaking build with gcc-5 - Fix opregion leak (Lucas) - Fix OA sysfs entry (Ashutosh) - Fix VM dma-resv lock (Brost) - Fix tile fini sequence (Brost) - Prevent UAF around preempt fence (Auld) - Fix DGFX display suspend/resume (Maarten) - Many Xe/Xe2 critical workarounds (Auld, Ngai-Mint, Bommu, Tejas, Daniele) - Fix devm/drmm issues (Daniele) - Fix missing workqueue destroy in xe_gt_pagefault (Stuart) - Drop HW fence pointer to HW fence ctx (Brost) - Free job before xe_exec_queue_put (Brost)" * tag 'drm-fixes-2024-08-24' of https://gitlab.freedesktop.org/drm/kernel: (35 commits) drm/xe: Free job before xe_exec_queue_put drm/xe: Drop HW fence pointer to HW fence ctx drm/xe: Fix missing workqueue destroy in xe_gt_pagefault drm/amdgpu: fix eGPU hotplug regression drm/amdgpu: Validate TA binary size drm/amdgpu/sdma5.2: limit wptr workaround to sdma 5.2.1 drm/amdgpu: fixing rlc firmware loading failure issue drm/xe/uc: Use devm to register cleanup that includes exec_queues drm/xe: use devm instead of drmm for managed bo drm/xe/xe2hpg: Add Wa_14021821874 drm/xe: fix WA 14018094691 drm/xe/xe2: Add Wa_15015404425 drm/xe/xe2: Make subsequent L2 flush sequential drm/xe/xe2lpg: Extend workaround 14021402888 drm/xe/xe2lpm: Extend Wa_16021639441 drm/xe/bmg: implement Wa_16023588340 drm/xe/oa/uapi: Make bit masks unsigned drm/xe/display: Make display suspend/resume work on discrete drm/xe: prevent UAF around preempt fence drm/xe: Fix tile fini sequence ...
2 parents d5afaf9 + 76f4618 commit 79a899e

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43 files changed

+334
-90
lines changed

drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -278,7 +278,7 @@ static int amdgpu_discovery_read_binary_from_mem(struct amdgpu_device *adev,
278278
msg = RREG32(mmMP0_SMN_C2PMSG_33);
279279
if (msg & 0x80000000)
280280
break;
281-
usleep_range(1000, 1100);
281+
msleep(1);
282282
}
283283
}
284284

drivers/gpu/drm/amd/amdgpu/amdgpu_psp_ta.c

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -166,6 +166,9 @@ static ssize_t ta_if_load_debugfs_write(struct file *fp, const char *buf, size_t
166166
if (ret)
167167
return -EFAULT;
168168

169+
if (ta_bin_len > PSP_1_MEG)
170+
return -EINVAL;
171+
169172
copy_pos += sizeof(uint32_t);
170173

171174
ta_bin = kzalloc(ta_bin_len, GFP_KERNEL);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -4116,6 +4116,7 @@ static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev)
41164116

41174117
static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
41184118
{
4119+
char fw_name[53];
41194120
char ucode_prefix[30];
41204121
const char *wks = "";
41214122
int err;
@@ -4149,8 +4150,8 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
41494150
amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_CE);
41504151

41514152
if (!amdgpu_sriov_vf(adev)) {
4152-
err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw,
4153-
"amdgpu/%s_rlc.bin", ucode_prefix);
4153+
snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", ucode_prefix);
4154+
err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
41544155
if (err)
41554156
goto out;
41564157

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

Lines changed: 10 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -176,14 +176,16 @@ static void sdma_v5_2_ring_set_wptr(struct amdgpu_ring *ring)
176176
DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
177177
ring->doorbell_index, ring->wptr << 2);
178178
WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
179-
/* SDMA seems to miss doorbells sometimes when powergating kicks in.
180-
* Updating the wptr directly will wake it. This is only safe because
181-
* we disallow gfxoff in begin_use() and then allow it again in end_use().
182-
*/
183-
WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR),
184-
lower_32_bits(ring->wptr << 2));
185-
WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI),
186-
upper_32_bits(ring->wptr << 2));
179+
if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(5, 2, 1)) {
180+
/* SDMA seems to miss doorbells sometimes when powergating kicks in.
181+
* Updating the wptr directly will wake it. This is only safe because
182+
* we disallow gfxoff in begin_use() and then allow it again in end_use().
183+
*/
184+
WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR),
185+
lower_32_bits(ring->wptr << 2));
186+
WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI),
187+
upper_32_bits(ring->wptr << 2));
188+
}
187189
} else {
188190
DRM_DEBUG("Not using doorbell -- "
189191
"mmSDMA%i_GFX_RB_WPTR == 0x%08x "

drivers/gpu/drm/i915/display/intel_dp_hdcp.c

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -39,7 +39,9 @@ static u32 transcoder_to_stream_enc_status(enum transcoder cpu_transcoder)
3939
static void intel_dp_hdcp_wait_for_cp_irq(struct intel_connector *connector,
4040
int timeout)
4141
{
42-
struct intel_hdcp *hdcp = &connector->hdcp;
42+
struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
43+
struct intel_dp *dp = &dig_port->dp;
44+
struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
4345
long ret;
4446

4547
#define C (hdcp->cp_irq_count_cached != atomic_read(&hdcp->cp_irq_count))

drivers/gpu/drm/msm/adreno/adreno_gpu.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -99,7 +99,7 @@ static int zap_shader_load_mdt(struct msm_gpu *gpu, const char *fwname,
9999
* was a bad idea, and is only provided for backwards
100100
* compatibility for older targets.
101101
*/
102-
return -ENODEV;
102+
return -ENOENT;
103103
}
104104

105105
if (IS_ERR(fw)) {

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1171,8 +1171,6 @@ static void dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc,
11711171

11721172
cstate->num_mixers = num_lm;
11731173

1174-
dpu_enc->connector = conn_state->connector;
1175-
11761174
for (i = 0; i < dpu_enc->num_phys_encs; i++) {
11771175
struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
11781176

@@ -1270,6 +1268,8 @@ static void dpu_encoder_virt_atomic_enable(struct drm_encoder *drm_enc,
12701268

12711269
dpu_enc->commit_done_timedout = false;
12721270

1271+
dpu_enc->connector = drm_atomic_get_new_connector_for_encoder(state, drm_enc);
1272+
12731273
cur_mode = &dpu_enc->base.crtc->state->adjusted_mode;
12741274

12751275
dpu_enc->wide_bus_en = dpu_encoder_is_widebus_enabled(drm_enc);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -308,8 +308,8 @@ static const u32 wb2_formats_rgb_yuv[] = {
308308
{ \
309309
.maxdwnscale = SSPP_UNITY_SCALE, \
310310
.maxupscale = SSPP_UNITY_SCALE, \
311-
.format_list = plane_formats_yuv, \
312-
.num_formats = ARRAY_SIZE(plane_formats_yuv), \
311+
.format_list = plane_formats, \
312+
.num_formats = ARRAY_SIZE(plane_formats), \
313313
.virt_format_list = plane_formats, \
314314
.virt_num_formats = ARRAY_SIZE(plane_formats), \
315315
}

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h

Lines changed: 2 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -31,24 +31,14 @@
3131
* @fmt: Pointer to format string
3232
*/
3333
#define DPU_DEBUG(fmt, ...) \
34-
do { \
35-
if (drm_debug_enabled(DRM_UT_KMS)) \
36-
DRM_DEBUG(fmt, ##__VA_ARGS__); \
37-
else \
38-
pr_debug(fmt, ##__VA_ARGS__); \
39-
} while (0)
34+
DRM_DEBUG_DRIVER(fmt, ##__VA_ARGS__)
4035

4136
/**
4237
* DPU_DEBUG_DRIVER - macro for hardware driver logging
4338
* @fmt: Pointer to format string
4439
*/
4540
#define DPU_DEBUG_DRIVER(fmt, ...) \
46-
do { \
47-
if (drm_debug_enabled(DRM_UT_DRIVER)) \
48-
DRM_ERROR(fmt, ##__VA_ARGS__); \
49-
else \
50-
pr_debug(fmt, ##__VA_ARGS__); \
51-
} while (0)
41+
DRM_DEBUG_DRIVER(fmt, ##__VA_ARGS__)
5242

5343
#define DPU_ERROR(fmt, ...) pr_err("[dpu error]" fmt, ##__VA_ARGS__)
5444
#define DPU_ERROR_RATELIMITED(fmt, ...) pr_err_ratelimited("[dpu error]" fmt, ##__VA_ARGS__)

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

Lines changed: 17 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -681,6 +681,9 @@ static int dpu_plane_prepare_fb(struct drm_plane *plane,
681681
new_state->fb, &layout);
682682
if (ret) {
683683
DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret);
684+
if (pstate->aspace)
685+
msm_framebuffer_cleanup(new_state->fb, pstate->aspace,
686+
pstate->needs_dirtyfb);
684687
return ret;
685688
}
686689

@@ -744,10 +747,9 @@ static int dpu_plane_atomic_check_pipe(struct dpu_plane *pdpu,
744747
min_src_size = MSM_FORMAT_IS_YUV(fmt) ? 2 : 1;
745748

746749
if (MSM_FORMAT_IS_YUV(fmt) &&
747-
(!pipe->sspp->cap->sblk->scaler_blk.len ||
748-
!pipe->sspp->cap->sblk->csc_blk.len)) {
750+
!pipe->sspp->cap->sblk->csc_blk.len) {
749751
DPU_DEBUG_PLANE(pdpu,
750-
"plane doesn't have scaler/csc for yuv\n");
752+
"plane doesn't have csc for yuv\n");
751753
return -EINVAL;
752754
}
753755

@@ -864,6 +866,10 @@ static int dpu_plane_atomic_check(struct drm_plane *plane,
864866

865867
max_linewidth = pdpu->catalog->caps->max_linewidth;
866868

869+
drm_rect_rotate(&pipe_cfg->src_rect,
870+
new_plane_state->fb->width, new_plane_state->fb->height,
871+
new_plane_state->rotation);
872+
867873
if ((drm_rect_width(&pipe_cfg->src_rect) > max_linewidth) ||
868874
_dpu_plane_calc_clk(&crtc_state->adjusted_mode, pipe_cfg) > max_mdp_clk_rate) {
869875
/*
@@ -913,6 +919,14 @@ static int dpu_plane_atomic_check(struct drm_plane *plane,
913919
r_pipe_cfg->dst_rect.x1 = pipe_cfg->dst_rect.x2;
914920
}
915921

922+
drm_rect_rotate_inv(&pipe_cfg->src_rect,
923+
new_plane_state->fb->width, new_plane_state->fb->height,
924+
new_plane_state->rotation);
925+
if (r_pipe->sspp)
926+
drm_rect_rotate_inv(&r_pipe_cfg->src_rect,
927+
new_plane_state->fb->width, new_plane_state->fb->height,
928+
new_plane_state->rotation);
929+
916930
ret = dpu_plane_atomic_check_pipe(pdpu, pipe, pipe_cfg, fmt, &crtc_state->adjusted_mode);
917931
if (ret)
918932
return ret;

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