@@ -76,6 +76,7 @@ struct xdma_hw_desc {
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#define XDMA_CHAN_CONTROL_W1S 0x8
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#define XDMA_CHAN_CONTROL_W1C 0xc
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#define XDMA_CHAN_STATUS 0x40
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+ #define XDMA_CHAN_STATUS_RC 0x44
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#define XDMA_CHAN_COMPLETED_DESC 0x48
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#define XDMA_CHAN_ALIGNMENTS 0x4c
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#define XDMA_CHAN_INTR_ENABLE 0x90
@@ -101,6 +102,7 @@ struct xdma_hw_desc {
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#define CHAN_CTRL_IE_MAGIC_STOPPED BIT(4)
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#define CHAN_CTRL_IE_IDLE_STOPPED BIT(6)
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#define CHAN_CTRL_IE_READ_ERROR GENMASK(13, 9)
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+ #define CHAN_CTRL_IE_WRITE_ERROR GENMASK(18, 14)
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#define CHAN_CTRL_IE_DESC_ERROR GENMASK(23, 19)
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#define CHAN_CTRL_NON_INCR_ADDR BIT(25)
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#define CHAN_CTRL_POLL_MODE_WB BIT(26)
@@ -111,8 +113,17 @@ struct xdma_hw_desc {
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CHAN_CTRL_IE_DESC_ALIGN_MISMATCH | \
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CHAN_CTRL_IE_MAGIC_STOPPED | \
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CHAN_CTRL_IE_READ_ERROR | \
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+ CHAN_CTRL_IE_WRITE_ERROR | \
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CHAN_CTRL_IE_DESC_ERROR)
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+ #define XDMA_CHAN_STATUS_MASK CHAN_CTRL_START
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+
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+ #define XDMA_CHAN_ERROR_MASK (CHAN_CTRL_IE_DESC_ALIGN_MISMATCH | \
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+ CHAN_CTRL_IE_MAGIC_STOPPED | \
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+ CHAN_CTRL_IE_READ_ERROR | \
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+ CHAN_CTRL_IE_WRITE_ERROR | \
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+ CHAN_CTRL_IE_DESC_ERROR)
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+
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/* bits of the channel interrupt enable mask */
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#define CHAN_IM_DESC_ERROR BIT(19)
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#define CHAN_IM_READ_ERROR BIT(9)
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