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Andy Yanmmind
Andy Yan
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mmind
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drm/rockchip: vop2: Set AXI id for rk3588
There are two AXI bus in vop2, windows attached on the same bus must have a unique channel YUV and RGB channel ID. The default IDs will conflict with each other on the rk3588, so they need to be reassigned. Fixes: 5a028e8 ("drm/rockchip: vop2: Add support for rk3588") Signed-off-by: Andy Yan <[email protected]> Tested-by: Derek Foreman <[email protected]> Tested-by: Detlev Casanova <[email protected]> Signed-off-by: Heiko Stuebner <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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‎drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1426,6 +1426,12 @@ static void vop2_plane_atomic_update(struct drm_plane *plane,
14261426
&fb->format->format,
14271427
afbc_en ? "AFBC" : "", &yrgb_mst);
14281428

1429+
if (vop2->data->soc_id > 3568) {
1430+
vop2_win_write(win, VOP2_WIN_AXI_BUS_ID, win->data->axi_bus_id);
1431+
vop2_win_write(win, VOP2_WIN_AXI_YRGB_R_ID, win->data->axi_yrgb_r_id);
1432+
vop2_win_write(win, VOP2_WIN_AXI_UV_R_ID, win->data->axi_uv_r_id);
1433+
}
1434+
14291435
if (vop2_cluster_window(win))
14301436
vop2_win_write(win, VOP2_WIN_AFBC_HALF_BLOCK_EN, half_block_en);
14311437

@@ -3353,6 +3359,10 @@ static struct reg_field vop2_cluster_regs[VOP2_WIN_MAX_REG] = {
33533359
[VOP2_WIN_Y2R_EN] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 8, 8),
33543360
[VOP2_WIN_R2Y_EN] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 9, 9),
33553361
[VOP2_WIN_CSC_MODE] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 10, 11),
3362+
[VOP2_WIN_AXI_YRGB_R_ID] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL2, 0, 3),
3363+
[VOP2_WIN_AXI_UV_R_ID] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL2, 5, 8),
3364+
/* RK3588 only, reserved bit on rk3568*/
3365+
[VOP2_WIN_AXI_BUS_ID] = REG_FIELD(RK3568_CLUSTER_CTRL, 13, 13),
33563366

33573367
/* Scale */
33583368
[VOP2_WIN_SCALE_YRGB_X] = REG_FIELD(RK3568_CLUSTER_WIN_SCL_FACTOR_YRGB, 0, 15),
@@ -3445,6 +3455,10 @@ static struct reg_field vop2_esmart_regs[VOP2_WIN_MAX_REG] = {
34453455
[VOP2_WIN_YMIRROR] = REG_FIELD(RK3568_SMART_CTRL1, 31, 31),
34463456
[VOP2_WIN_COLOR_KEY] = REG_FIELD(RK3568_SMART_COLOR_KEY_CTRL, 0, 29),
34473457
[VOP2_WIN_COLOR_KEY_EN] = REG_FIELD(RK3568_SMART_COLOR_KEY_CTRL, 31, 31),
3458+
[VOP2_WIN_AXI_YRGB_R_ID] = REG_FIELD(RK3568_SMART_CTRL1, 4, 8),
3459+
[VOP2_WIN_AXI_UV_R_ID] = REG_FIELD(RK3568_SMART_CTRL1, 12, 16),
3460+
/* RK3588 only, reserved register on rk3568 */
3461+
[VOP2_WIN_AXI_BUS_ID] = REG_FIELD(RK3588_SMART_AXI_CTRL, 1, 1),
34483462

34493463
/* Scale */
34503464
[VOP2_WIN_SCALE_YRGB_X] = REG_FIELD(RK3568_SMART_REGION0_SCL_FACTOR_YRGB, 0, 15),

‎drivers/gpu/drm/rockchip/rockchip_drm_vop2.h

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -78,6 +78,9 @@ enum vop2_win_regs {
7878
VOP2_WIN_COLOR_KEY,
7979
VOP2_WIN_COLOR_KEY_EN,
8080
VOP2_WIN_DITHER_UP,
81+
VOP2_WIN_AXI_BUS_ID,
82+
VOP2_WIN_AXI_YRGB_R_ID,
83+
VOP2_WIN_AXI_UV_R_ID,
8184

8285
/* scale regs */
8386
VOP2_WIN_SCALE_YRGB_X,
@@ -149,6 +152,10 @@ struct vop2_win_data {
149152
unsigned int layer_sel_id;
150153
uint64_t feature;
151154

155+
uint8_t axi_bus_id;
156+
uint8_t axi_yrgb_r_id;
157+
uint8_t axi_uv_r_id;
158+
152159
unsigned int max_upscale_factor;
153160
unsigned int max_downscale_factor;
154161
const u8 dly[VOP2_DLY_MODE_MAX];
@@ -319,6 +326,7 @@ enum dst_factor_mode {
319326

320327
#define RK3568_CLUSTER_WIN_CTRL0 0x00
321328
#define RK3568_CLUSTER_WIN_CTRL1 0x04
329+
#define RK3568_CLUSTER_WIN_CTRL2 0x08
322330
#define RK3568_CLUSTER_WIN_YRGB_MST 0x10
323331
#define RK3568_CLUSTER_WIN_CBR_MST 0x14
324332
#define RK3568_CLUSTER_WIN_VIR 0x18
@@ -341,6 +349,7 @@ enum dst_factor_mode {
341349
/* (E)smart register definition, offset relative to window base */
342350
#define RK3568_SMART_CTRL0 0x00
343351
#define RK3568_SMART_CTRL1 0x04
352+
#define RK3588_SMART_AXI_CTRL 0x08
344353
#define RK3568_SMART_REGION0_CTRL 0x10
345354
#define RK3568_SMART_REGION0_YRGB_MST 0x14
346355
#define RK3568_SMART_REGION0_CBR_MST 0x18

‎drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

Lines changed: 25 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -395,7 +395,7 @@ static const struct vop2_video_port_data rk3588_vop_video_ports[] = {
395395
* AXI1 is a read only bus.
396396
*
397397
* Every window on a AXI bus must assigned two unique
398-
* read id(yrgb_id/uv_id, valid id are 0x1~0xe).
398+
* read id(yrgb_r_id/uv_r_id, valid id are 0x1~0xe).
399399
*
400400
* AXI0:
401401
* Cluster0/1, Esmart0/1, WriteBack
@@ -415,6 +415,9 @@ static const struct vop2_win_data rk3588_vop_win_data[] = {
415415
.layer_sel_id = 0,
416416
.supported_rotations = DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270 |
417417
DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y,
418+
.axi_bus_id = 0,
419+
.axi_yrgb_r_id = 2,
420+
.axi_uv_r_id = 3,
418421
.max_upscale_factor = 4,
419422
.max_downscale_factor = 4,
420423
.dly = { 4, 26, 29 },
@@ -431,6 +434,9 @@ static const struct vop2_win_data rk3588_vop_win_data[] = {
431434
.supported_rotations = DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270 |
432435
DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y,
433436
.type = DRM_PLANE_TYPE_PRIMARY,
437+
.axi_bus_id = 0,
438+
.axi_yrgb_r_id = 6,
439+
.axi_uv_r_id = 7,
434440
.max_upscale_factor = 4,
435441
.max_downscale_factor = 4,
436442
.dly = { 4, 26, 29 },
@@ -446,6 +452,9 @@ static const struct vop2_win_data rk3588_vop_win_data[] = {
446452
.supported_rotations = DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270 |
447453
DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y,
448454
.type = DRM_PLANE_TYPE_PRIMARY,
455+
.axi_bus_id = 1,
456+
.axi_yrgb_r_id = 2,
457+
.axi_uv_r_id = 3,
449458
.max_upscale_factor = 4,
450459
.max_downscale_factor = 4,
451460
.dly = { 4, 26, 29 },
@@ -461,6 +470,9 @@ static const struct vop2_win_data rk3588_vop_win_data[] = {
461470
.supported_rotations = DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270 |
462471
DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y,
463472
.type = DRM_PLANE_TYPE_PRIMARY,
473+
.axi_bus_id = 1,
474+
.axi_yrgb_r_id = 6,
475+
.axi_uv_r_id = 7,
464476
.max_upscale_factor = 4,
465477
.max_downscale_factor = 4,
466478
.dly = { 4, 26, 29 },
@@ -475,6 +487,9 @@ static const struct vop2_win_data rk3588_vop_win_data[] = {
475487
.layer_sel_id = 2,
476488
.supported_rotations = DRM_MODE_REFLECT_Y,
477489
.type = DRM_PLANE_TYPE_OVERLAY,
490+
.axi_bus_id = 0,
491+
.axi_yrgb_r_id = 0x0a,
492+
.axi_uv_r_id = 0x0b,
478493
.max_upscale_factor = 8,
479494
.max_downscale_factor = 8,
480495
.dly = { 23, 45, 48 },
@@ -488,6 +503,9 @@ static const struct vop2_win_data rk3588_vop_win_data[] = {
488503
.layer_sel_id = 3,
489504
.supported_rotations = DRM_MODE_REFLECT_Y,
490505
.type = DRM_PLANE_TYPE_OVERLAY,
506+
.axi_bus_id = 0,
507+
.axi_yrgb_r_id = 0x0c,
508+
.axi_uv_r_id = 0x01,
491509
.max_upscale_factor = 8,
492510
.max_downscale_factor = 8,
493511
.dly = { 23, 45, 48 },
@@ -501,6 +519,9 @@ static const struct vop2_win_data rk3588_vop_win_data[] = {
501519
.layer_sel_id = 6,
502520
.supported_rotations = DRM_MODE_REFLECT_Y,
503521
.type = DRM_PLANE_TYPE_OVERLAY,
522+
.axi_bus_id = 1,
523+
.axi_yrgb_r_id = 0x0a,
524+
.axi_uv_r_id = 0x0b,
504525
.max_upscale_factor = 8,
505526
.max_downscale_factor = 8,
506527
.dly = { 23, 45, 48 },
@@ -514,6 +535,9 @@ static const struct vop2_win_data rk3588_vop_win_data[] = {
514535
.layer_sel_id = 7,
515536
.supported_rotations = DRM_MODE_REFLECT_Y,
516537
.type = DRM_PLANE_TYPE_OVERLAY,
538+
.axi_bus_id = 1,
539+
.axi_yrgb_r_id = 0x0c,
540+
.axi_uv_r_id = 0x0d,
517541
.max_upscale_factor = 8,
518542
.max_downscale_factor = 8,
519543
.dly = { 23, 45, 48 },

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