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Merge tag 'pci-v6.15-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci
Pull pci updates from Bjorn Helgaas: "Enumeration: - Enable Configuration RRS SV, which makes device readiness visible, early instead of during child bus scanning (Bjorn Helgaas) - Log debug messages about reset methods being used (Bjorn Helgaas) - Avoid reset when it has been disabled via sysfs (Nishanth Aravamudan) - Add common pci-ep-bus.yaml schema for exporting several peripherals of a single PCI function via devicetree (Andrea della Porta) - Create DT nodes for PCI host bridges to enable loading device tree overlays to create platform devices for PCI devices that have several features that require multiple drivers (Herve Codina) Resource management: - Enlarge devres table[] to accommodate bridge windows, ROM, IOV BARs, etc., and validate BAR index in devres interfaces (Philipp Stanner) - Fix typo that repeatedly distributed resources to a bridge instead of iterating over subordinate bridges, which resulted in too little space to assign some BARs (Kai-Heng Feng) - Relax bridge window tail sizing for optional resources, e.g., IOV BARs, to avoid failures when removing and re-adding devices (Ilpo Järvinen) - Allow drivers to enable devices even if we haven't assigned optional IOV resources to them (Ilpo Järvinen) - Rework handling of optional resources (IOV BARs, ROMs) to reduce failures if we can't allocate them (Ilpo Järvinen) - Fix a NULL dereference in the SR-IOV VF creation error path (Shay Drory) - Fix s390 mmio_read/write syscalls, which didn't cause page faults in some cases, which broke vfio-pci lazy mapping on first access (Niklas Schnelle) - Add pdev->non_mappable_bars to replace CONFIG_VFIO_PCI_MMAP, which was disabled only for s390 (Niklas Schnelle) - Support mmap of PCI resources on s390 except for ISM devices (Niklas Schnelle) ASPM: - Delay pcie_link_state deallocation to avoid dangling pointers that cause invalid references during hot-unplug (Daniel Stodden) Power management: - Allow PCI bridges to go to D3Hot when suspending on all non-x86 systems (Manivannan Sadhasivam) Power control: - Create pwrctrl devices in pci_scan_device() to make it more symmetric with pci_pwrctrl_unregister() and make pwrctrl devices for PCI bridges possible (Manivannan Sadhasivam) - Unregister pwrctrl devices in pci_destroy_dev() so DOE, ASPM, etc. can still access devices after pci_stop_dev() (Manivannan Sadhasivam) - If there's a pwrctrl device for a PCI device, skip scanning it because the pwrctrl core will rescan the bus after the device is powered on (Manivannan Sadhasivam) - Add a pwrctrl driver for PCI slots based on voltage regulators described via devicetree (Manivannan Sadhasivam) Bandwidth control: - Add set_pcie_speed.sh to TEST_PROGS to fix issue when executing the set_pcie_cooling_state.sh test case (Yi Lai) - Avoid a NULL pointer dereference when we run out of bus numbers to assign for a bridge secondary bus (Lukas Wunner) Hotplug: - Drop superfluous pci_hotplug_slot_list, try_module_get() calls, and NULL pointer checks (Lukas Wunner) - Drop shpchp module init/exit logging, replace shpchp dbg() with ctrl_dbg(), and remove unused dbg(), err(), info(), warn() wrappers (Ilpo Järvinen) - Drop 'shpchp_debug' module parameter in favor of standard dynamic debugging (Ilpo Järvinen) - Drop unused cpcihp .get_power(), .set_power() function pointers (Guilherme Giacomo Simoes) - Disable hotplug interrupts in portdrv only when pciehp is not enabled to avoid issuing two hotplug commands too close together (Feng Tang) - Skip pciehp 'device replaced' check if the device has been removed to address a deadlock when resuming after a device was removed during system sleep (Lukas Wunner) - Don't enable pciehp hotplug interupt when resuming in poll mode (Ilpo Järvinen) Virtualization: - Fix bugs in 'pci=config_acs=' kernel command line parameter (Tushar Dave) DOE: - Expose supported DOE features via sysfs (Alistair Francis) - Allow DOE support to be enabled even if CXL isn't enabled (Alistair Francis) Endpoint framework: - Convert PCI device data so pci-epf-test works correctly on big-endian endpoint systems (Niklas Cassel) - Add BAR_RESIZABLE type to endpoint framework and add DWC core support for EPF drivers to set BAR_RESIZABLE type and size (Niklas Cassel) - Fix pci-epf-test double free that causes an oops if the host reboots and PERST# deassertion restarts endpoint BAR allocation (Christian Bruel) - Fix endpoint BAR testing so tests can skip disabled BARs instead of reporting them as failures (Niklas Cassel) - Widen endpoint test BAR size variable to accommodate BARs larger than INT_MAX (Niklas Cassel) - Remove unused tools 'pci' build target left over after moving tests to tools/testing/selftests/pci_endpoint (Jianfeng Liu) Altera PCIe controller driver: - Add DT binding and driver support for Agilex family (P-Tile, F-Tile, R-Tile) (Matthew Gerlach and D M, Sharath Kumar) AMD MDB PCIe controller driver: - Add DT binding and driver for AMD MDB (Multimedia DMA Bridge) (Thippeswamy Havalige) Broadcom STB PCIe controller driver: - Add BCM2712 MSI-X DT binding and interrupt controller drivers and add softdep on irq_bcm2712_mip driver to ensure that it is loaded first (Stanimir Varbanov) - Expand inbound window map to 64GB so it can accommodate BCM2712 (Stanimir Varbanov) - Add BCM2712 support and DT updates (Stanimir Varbanov) - Apply link speed restriction before bringing link up, not after (Jim Quinlan) - Update Max Link Speed in Link Capabilities via the internal writable register, not the read-only config register (Jim Quinlan) - Handle regulator_bulk_get() error to avoid panic when we call regulator_bulk_free() later (Jim Quinlan) - Disable regulators only when removing the bus immediately below a Root Port because we don't support regulators deeper in the hierarchy (Jim Quinlan) - Make const read-only arrays static (Colin Ian King) Cadence PCIe endpoint driver: - Correct MSG TLP generation so endpoints can generate INTx messages (Hans Zhang) Freescale i.MX6 PCIe controller driver: - Identify the second controller on i.MX8MQ based on devicetree 'linux,pci-domain' instead of DBI 'reg' address (Richard Zhu) - Remove imx_pcie_cpu_addr_fixup() since dwc core can now derive the ATU input address (using parent_bus_offset) from devicetree (Frank Li) Freescale Layerscape PCIe controller driver: - Drop deprecated 'num-ib-windows' and 'num-ob-windows' and unnecessary 'status' from example (Krzysztof Kozlowski) - Correct the syscon_regmap_lookup_by_phandle_args("fsl,pcie-scfg") arg_count to fix probe failure on LS1043A (Ioana Ciornei) HiSilicon STB PCIe controller driver: - Call phy_exit() to clean up if histb_pcie_probe() fails (Christophe JAILLET) Intel Gateway PCIe controller driver: - Remove intel_pcie_cpu_addr() since dwc core can now derive the ATU input address (using parent_bus_offset) from devicetree (Frank Li) Intel VMD host bridge driver: - Convert vmd_dev.cfg_lock from spinlock_t to raw_spinlock_t so pci_ops.read() will never sleep, even on PREEMPT_RT where spinlock_t becomes a sleepable lock, to avoid calling a sleeping function from invalid context (Ryo Takakura) MediaTek PCIe Gen3 controller driver: - Remove leftover mac_reset assert for Airoha EN7581 SoC (Lorenzo Bianconi) - Add EN7581 PBUS controller 'mediatek,pbus-csr' DT property and program host bridge memory aperture to this syscon node (Lorenzo Bianconi) Qualcomm PCIe controller driver: - Add qcom,pcie-ipq5332 binding (Varadarajan Narayanan) - Add qcom i.MX8QM and i.MX8QXP/DXP optional DMA interrupt (Alexander Stein) - Add optional dma-coherent DT property for Qualcomm SA8775P (Dmitry Baryshkov) - Make DT iommu property required for SA8775P and prohibited for SDX55 (Dmitry Baryshkov) - Add DT IOMMU and DMA-related properties for Qualcomm SM8450 (Dmitry Baryshkov) - Add endpoint DT properties for SAR2130P and enable endpoint mode in driver (Dmitry Baryshkov) - Describe endpoint BAR0 and BAR2 as 64-bit only and BAR1 and BAR3 as RESERVED (Manivannan Sadhasivam) Rockchip DesignWare PCIe controller driver: - Describe rk3568 and rk3588 BARs as Resizable, not Fixed (Niklas Cassel) Synopsys DesignWare PCIe controller driver: - Add debugfs-based Silicon Debug, Error Injection, Statistical Counter support for DWC (Shradha Todi) - Add debugfs property to expose LTSSM status of DWC PCIe link (Hans Zhang) - Add Rockchip support for DWC debugfs features (Niklas Cassel) - Add dw_pcie_parent_bus_offset() to look up the parent bus address of a specified 'reg' property and return the offset from the CPU physical address (Frank Li) - Use dw_pcie_parent_bus_offset() to derive CPU -> ATU addr offset via 'reg[config]' for host controllers and 'reg[addr_space]' for endpoint controllers (Frank Li) - Apply struct dw_pcie.parent_bus_offset in ATU users to remove use of .cpu_addr_fixup() when programming ATU (Frank Li) TI J721E PCIe driver: - Correct the 'link down' interrupt bit for J784S4 (Siddharth Vadapalli) TI Keystone PCIe controller driver: - Describe AM65x BARs 2 and 5 as Resizable (not Fixed) and reduce alignment requirement from 1MB to 64KB (Niklas Cassel) Xilinx Versal CPM PCIe controller driver: - Free IRQ domain in probe error path to avoid leaking it (Thippeswamy Havalige) - Add DT .compatible "xlnx,versal-cpm5nc-host" and driver support for Versal Net CPM5NC Root Port controller (Thippeswamy Havalige) - Add driver support for CPM5_HOST1 (Thippeswamy Havalige) Miscellaneous: - Convert fsl,mpc83xx-pcie binding to YAML (J. Neuschäfer) - Use for_each_available_child_of_node_scoped() to simplify apple, kirin, mediatek, mt7621, tegra drivers (Zhang Zekun)" * tag 'pci-v6.15-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci: (197 commits) PCI: layerscape: Fix arg_count to syscon_regmap_lookup_by_phandle_args() PCI: j721e: Fix the value of .linkdown_irq_regfield for J784S4 misc: pci_endpoint_test: Add support for PCITEST_IRQ_TYPE_AUTO PCI: endpoint: pci-epf-test: Expose supported IRQ types in CAPS register PCI: dw-rockchip: Endpoint mode cannot raise INTx interrupts PCI: endpoint: Add intx_capable to epc_features struct dt-bindings: PCI: Add common schema for devices accessible through PCI BARs PCI: intel-gw: Remove intel_pcie_cpu_addr() PCI: imx6: Remove imx_pcie_cpu_addr_fixup() PCI: dwc: Use parent_bus_offset to remove need for .cpu_addr_fixup() PCI: dwc: ep: Ensure proper iteration over outbound map windows PCI: dwc: ep: Use devicetree 'reg[addr_space]' to derive CPU -> ATU addr offset PCI: dwc: ep: Consolidate devicetree handling in dw_pcie_ep_get_resources() PCI: dwc: ep: Call epc_create() early in dw_pcie_ep_init() PCI: dwc: Use devicetree 'reg[config]' to derive CPU -> ATU addr offset PCI: dwc: Add dw_pcie_parent_bus_offset() checking and debug PCI: dwc: Add dw_pcie_parent_bus_offset() PCI/bwctrl: Fix NULL pointer dereference on bus number exhaustion PCI: xilinx-cpm: Add cpm_csr register mapping for CPM5_HOST1 variant PCI: brcmstb: Make const read-only arrays static ...
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‎Documentation/ABI/testing/debugfs-dwc-pcie

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What: /sys/kernel/debug/dwc_pcie_<dev>/rasdes_debug/lane_detect
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Date: February 2025
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Contact: Shradha Todi <[email protected]>
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Description: (RW) Write the lane number to be checked for detection. Read
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will return whether PHY indicates receiver detection on the
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selected lane. The default selected lane is Lane0.
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What: /sys/kernel/debug/dwc_pcie_<dev>/rasdes_debug/rx_valid
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Date: February 2025
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Contact: Shradha Todi <[email protected]>
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Description: (RW) Write the lane number to be checked as valid or invalid.
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Read will return the status of PIPE RXVALID signal of the
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selected lane. The default selected lane is Lane0.
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What: /sys/kernel/debug/dwc_pcie_<dev>/rasdes_err_inj/<error>
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Date: February 2025
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Contact: Shradha Todi <[email protected]>
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Description: The "rasdes_err_inj" is a directory which can be used to inject
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errors into the system. The possible errors that can be injected
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are:
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1) tx_lcrc - TLP LCRC error injection TX Path
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2) b16_crc_dllp - 16b CRC error injection of ACK/NAK DLLP
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3) b16_crc_upd_fc - 16b CRC error injection of Update-FC DLLP
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4) tx_ecrc - TLP ECRC error injection TX Path
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5) fcrc_tlp - TLP's FCRC error injection TX Path
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6) parity_tsos - Parity error of TSOS
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7) parity_skpos - Parity error on SKPOS
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8) rx_lcrc - LCRC error injection RX Path
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9) rx_ecrc - ECRC error injection RX Path
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10) tlp_err_seq - TLPs SEQ# error
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11) ack_nak_dllp_seq - DLLPS ACK/NAK SEQ# error
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12) ack_nak_dllp - ACK/NAK DLLPs transmission block
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13) upd_fc_dllp - UpdateFC DLLPs transmission block
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14) nak_dllp - Always transmission for NAK DLLP
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15) inv_sync_hdr_sym - Invert SYNC header
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16) com_pad_ts1 - COM/PAD TS1 order set
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17) com_pad_ts2 - COM/PAD TS2 order set
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18) com_fts - COM/FTS FTS order set
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19) com_idl - COM/IDL E-idle order set
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20) end_edb - END/EDB symbol
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21) stp_sdp - STP/SDP symbol
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22) com_skp - COM/SKP SKP order set
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23) posted_tlp_hdr - Posted TLP Header credit value control
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24) non_post_tlp_hdr - Non-Posted TLP Header credit value control
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25) cmpl_tlp_hdr - Completion TLP Header credit value control
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26) posted_tlp_data - Posted TLP Data credit value control
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27) non_post_tlp_data - Non-Posted TLP Data credit value control
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28) cmpl_tlp_data - Completion TLP Data credit value control
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29) duplicate_tlp - Generates duplicate TLPs
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30) nullified_tlp - Generates Nullified TLPs
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(WO) Write to the attribute will prepare controller to inject
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the respective error in the next transmission of data.
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Parameter required to write will change in the following ways:
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- Errors 9 and 10 are sequence errors. The write command:
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echo <count> <diff> > /sys/kernel/debug/dwc_pcie_<dev>/rasdes_err_inj/<error>
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<count>
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Number of errors to be injected
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<diff>
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The difference to add or subtract from natural
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sequence number to generate sequence error.
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Allowed range from -4095 to 4095
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- Errors 23 to 28 are credit value error insertions. The write
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command:
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echo <count> <diff> <vc> > /sys/kernel/debug/dwc_pcie_<dev>/rasdes_err_inj/<error>
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<count>
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Number of errors to be injected
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<diff>
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The difference to add or subtract from UpdateFC
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credit value. Allowed range from -4095 to 4095
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<vc>
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Target VC number
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- All other errors. The write command:
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echo <count> > /sys/kernel/debug/dwc_pcie_<dev>/rasdes_err_inj/<error>
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<count>
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Number of errors to be injected
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What: /sys/kernel/debug/dwc_pcie_<dev>/rasdes_event_counters/<event>/counter_enable
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Date: February 2025
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Contact: Shradha Todi <[email protected]>
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Description: The "rasdes_event_counters" is the directory which can be used
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to collect statistical data about the number of times a certain
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event has occurred in the controller. The list of possible
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events are:
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1) EBUF Overflow
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2) EBUF Underrun
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3) Decode Error
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4) Running Disparity Error
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5) SKP OS Parity Error
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6) SYNC Header Error
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7) Rx Valid De-assertion
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8) CTL SKP OS Parity Error
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9) 1st Retimer Parity Error
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10) 2nd Retimer Parity Error
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11) Margin CRC and Parity Error
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12) Detect EI Infer
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13) Receiver Error
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14) RX Recovery Req
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15) N_FTS Timeout
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16) Framing Error
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17) Deskew Error
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18) Framing Error In L0
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19) Deskew Uncompleted Error
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20) Bad TLP
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21) LCRC Error
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22) Bad DLLP
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23) Replay Number Rollover
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24) Replay Timeout
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25) Rx Nak DLLP
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26) Tx Nak DLLP
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27) Retry TLP
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28) FC Timeout
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29) Poisoned TLP
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30) ECRC Error
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31) Unsupported Request
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32) Completer Abort
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33) Completion Timeout
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34) EBUF SKP Add
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35) EBUF SKP Del
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(RW) Write 1 to enable the event counter and write 0 to disable
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the event counter. Read will return whether the counter is
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currently enabled or disabled. Counter is disabled by default.
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What: /sys/kernel/debug/dwc_pcie_<dev>/rasdes_event_counters/<event>/counter_value
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Date: February 2025
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Contact: Shradha Todi <[email protected]>
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Description: (RO) Read will return the current value of the event counter.
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To reset the counter, counter should be disabled first and then
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enabled back using the "counter_enable" attribute.
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What: /sys/kernel/debug/dwc_pcie_<dev>/rasdes_event_counters/<event>/lane_select
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Date: February 2025
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Contact: Shradha Todi <[email protected]>
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Description: (RW) Some lanes in the event list are lane specific events.
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These include events from 1 to 11, as well as, 34 and 35. Write
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the lane number for which you wish the counter to be enabled,
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disabled, or value dumped. Read will return the current
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selected lane number. Lane0 is selected by default.
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What: /sys/kernel/debug/dwc_pcie_<dev>/ltssm_status
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Date: February 2025
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Contact: Hans Zhang <[email protected]>
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Description: (RO) Read will return the current PCIe LTSSM state in both
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string and raw value.

‎Documentation/ABI/testing/sysfs-bus-pci

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enclosure-specific indications "specific0" to "specific7",
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hence the corresponding led class devices are unavailable if
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the DSM interface is used.
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What: /sys/bus/pci/devices/.../doe_features
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Date: March 2025
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Contact: Linux PCI developers <[email protected]>
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Description:
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This directory contains a list of the supported Data Object
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Exchange (DOE) features. The features are the file name.
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The contents of each file is the raw Vendor ID and data
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object feature values.
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The value comes from the device and specifies the vendor and
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data object type supported. The lower (RHS of the colon) is
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the data object type in hex. The upper (LHS of the colon)
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is the vendor ID.
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As all DOE devices must support the DOE discovery feature,
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if DOE is supported you will at least see the doe_discovery
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file, with this contents:
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# cat doe_features/doe_discovery
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0001:00
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If the device supports other features you will see other
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files as well. For example if CMA/SPDM and secure CMA/SPDM
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are supported the doe_features directory will look like
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this:
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# ls doe_features
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0001:01 0001:02 doe_discovery

‎Documentation/PCI/endpoint/pci-endpoint.rst

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The PCI controller driver can then create a new EPC device by invoking
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devm_pci_epc_create()/pci_epc_create().
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* devm_pci_epc_destroy()/pci_epc_destroy()
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* pci_epc_destroy()
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The PCI controller driver can destroy the EPC device created by either
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devm_pci_epc_create() or pci_epc_create() using devm_pci_epc_destroy() or
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pci_epc_destroy().
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The PCI controller driver can destroy the EPC device created by
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pci_epc_create() using pci_epc_destroy().
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* pci_epc_linkup()
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‎Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2712-msix.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm2712-msix.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Broadcom bcm2712 MSI-X Interrupt Peripheral support
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maintainers:
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- Stanimir Varbanov <[email protected]>
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description:
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This interrupt controller is used to provide interrupt vectors to the
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generic interrupt controller (GIC) on bcm2712. It will be used as
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external MSI-X controller for PCIe root complex.
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allOf:
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- $ref: /schemas/interrupt-controller/msi-controller.yaml#
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properties:
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compatible:
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const: brcm,bcm2712-mip
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reg:
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items:
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- description: Base register address
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- description: PCIe message address
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"#msi-cells":
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const: 0
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brcm,msi-offset:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: Shift the allocated MSI's.
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unevaluatedProperties: false
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required:
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- compatible
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- reg
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- msi-controller
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- msi-ranges
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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axi {
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#address-cells = <2>;
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#size-cells = <2>;
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msi-controller@1000130000 {
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compatible = "brcm,bcm2712-mip";
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reg = <0x10 0x00130000 0x00 0xc0>,
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<0xff 0xfffff000 0x00 0x1000>;
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msi-controller;
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#msi-cells = <0>;
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msi-ranges = <&gicv2 GIC_SPI 128 IRQ_TYPE_EDGE_RISING 64>;
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};
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};

‎Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml

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properties:
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compatible:
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description: Each family of socfpga has its own implementation of the
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PCI controller. The altr,pcie-root-port-1.0 is used for the Cyclone5
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family of chips. The Stratix10 family of chips is supported by the
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altr,pcie-root-port-2.0. The Agilex family of chips has three,
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non-register compatible, variants of PCIe Hard IP referred to as the
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F-Tile, P-Tile, and R-Tile, depending on the specific chip instance.
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enum:
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- altr,pcie-root-port-1.0
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- altr,pcie-root-port-2.0
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- altr,pcie-root-port-3.0-f-tile
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- altr,pcie-root-port-3.0-p-tile
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- altr,pcie-root-port-3.0-r-tile
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reg:
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items:

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