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Merge tag 'drm-next-2025-01-27' of https://gitlab.freedesktop.org/drm/kernel
Pull drm fixes from Simona Vetter: "cgroup: - fix Koncfig fallout from new dmem controller Driver Changes: - v3d NULL pointer regression fix in fence signalling race - virtio: uaf in dma_buf free path - xlnx: fix kerneldoc - bochs: fix double-free on driver removal - zynqmp: add missing locking to DP bridge driver - amdgpu fixes all over: - documentation, display, sriov, various hw block drivers - use drm/sched helper - mark some debug module options as unsafe - amdkfd: mark some debug module options as unsafe, trap handler updates, fix partial migration handling DRM core: - fix fbdev Kconfig select rules, improve tiled-based display support" * tag 'drm-next-2025-01-27' of https://gitlab.freedesktop.org/drm/kernel: (40 commits) drm/amd/display: Optimize cursor position updates drm/amd/display: Add hubp cache reset when powergating drm/amd/amdgpu: Enable scratch data dump for mes 12 drm/amd: Clarify kdoc for amdgpu.gttsize drm/amd/amdgpu: Prevent null pointer dereference in GPU bandwidth calculation drm/amd/display: Fix error pointers in amdgpu_dm_crtc_mem_type_changed drm/amdgpu: fix ring timeout issue in gfx10 sr-iov environment drm/amd/pm: Fix smu v13.0.6 caps initialization drm/amd/pm: Refactor SMU 13.0.6 SDMA reset firmware version checks revert "drm/amdgpu/pm: add definition PPSMC_MSG_ResetSDMA2" revert "drm/amdgpu/pm: Implement SDMA queue reset for different asic" drm/amd/pm: Add capability flags for SMU v13.0.6 drm/amd/display: fix SUBVP DC_DEBUG_MASK documentation drm/amd/display: fix CEC DC_DEBUG_MASK documentation drm/amdgpu: fix the PCIe lanes reporting in the INFO IOCTL drm/amdgpu: cache gpu pcie link width drm/amd/display: mark static functions noinline_for_stack drm/amdkfd: Clear MODE.VSKIP in gfx9 trap handler drm/amdgpu: Refine ip detection log message drm/amdgpu: Add handler for SDMA context empty ...
2 parents 9629d83 + 64179a1 commit 7d6e5b5

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‎Documentation/gpu/zynqmp.rst‎

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -144,6 +144,4 @@ Internals
144144

145145
.. kernel-doc:: drivers/gpu/drm/xlnx/zynqmp_dp.c
146146

147-
.. kernel-doc:: drivers/gpu/drm/xlnx/zynqmp_dpsub.c
148-
149147
.. kernel-doc:: drivers/gpu/drm/xlnx/zynqmp_kms.c

‎drivers/gpu/drm/Kconfig‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -294,6 +294,7 @@ config DRM_TTM_HELPER
294294
tristate
295295
depends on DRM
296296
select DRM_TTM
297+
select DRM_KMS_HELPER if DRM_FBDEV_EMULATION
297298
select FB_CORE if DRM_FBDEV_EMULATION
298299
select FB_SYSMEM_HELPERS_DEFERRED if DRM_FBDEV_EMULATION
299300
help
@@ -302,6 +303,7 @@ config DRM_TTM_HELPER
302303
config DRM_GEM_DMA_HELPER
303304
tristate
304305
depends on DRM
306+
select DRM_KMS_HELPER if DRM_FBDEV_EMULATION
305307
select FB_CORE if DRM_FBDEV_EMULATION
306308
select FB_DMAMEM_HELPERS_DEFERRED if DRM_FBDEV_EMULATION
307309
help
@@ -310,6 +312,7 @@ config DRM_GEM_DMA_HELPER
310312
config DRM_GEM_SHMEM_HELPER
311313
tristate
312314
depends on DRM && MMU
315+
select DRM_KMS_HELPER if DRM_FBDEV_EMULATION
313316
select FB_CORE if DRM_FBDEV_EMULATION
314317
select FB_SYSMEM_HELPERS_DEFERRED if DRM_FBDEV_EMULATION
315318
help

‎drivers/gpu/drm/amd/amdgpu/amdgpu_device.c‎

Lines changed: 122 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -2365,8 +2365,8 @@ int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
23652365
break;
23662366
}
23672367

2368-
DRM_INFO("add ip block number %d <%s>\n", adev->num_ip_blocks,
2369-
ip_block_version->funcs->name);
2368+
dev_info(adev->dev, "detected ip block number %d <%s>\n",
2369+
adev->num_ip_blocks, ip_block_version->funcs->name);
23702370

23712371
adev->ip_blocks[adev->num_ip_blocks].adev = adev;
23722372

@@ -6157,6 +6157,44 @@ static void amdgpu_device_partner_bandwidth(struct amdgpu_device *adev,
61576157
}
61586158
}
61596159

6160+
/**
6161+
* amdgpu_device_gpu_bandwidth - find the bandwidth of the GPU
6162+
*
6163+
* @adev: amdgpu_device pointer
6164+
* @speed: pointer to the speed of the link
6165+
* @width: pointer to the width of the link
6166+
*
6167+
* Evaluate the hierarchy to find the speed and bandwidth capabilities of the
6168+
* AMD dGPU which may be a virtual upstream bridge.
6169+
*/
6170+
static void amdgpu_device_gpu_bandwidth(struct amdgpu_device *adev,
6171+
enum pci_bus_speed *speed,
6172+
enum pcie_link_width *width)
6173+
{
6174+
struct pci_dev *parent = adev->pdev;
6175+
6176+
if (!speed || !width)
6177+
return;
6178+
6179+
parent = pci_upstream_bridge(parent);
6180+
if (parent && parent->vendor == PCI_VENDOR_ID_ATI) {
6181+
/* use the upstream/downstream switches internal to dGPU */
6182+
*speed = pcie_get_speed_cap(parent);
6183+
*width = pcie_get_width_cap(parent);
6184+
while ((parent = pci_upstream_bridge(parent))) {
6185+
if (parent->vendor == PCI_VENDOR_ID_ATI) {
6186+
/* use the upstream/downstream switches internal to dGPU */
6187+
*speed = pcie_get_speed_cap(parent);
6188+
*width = pcie_get_width_cap(parent);
6189+
}
6190+
}
6191+
} else {
6192+
/* use the device itself */
6193+
*speed = pcie_get_speed_cap(adev->pdev);
6194+
*width = pcie_get_width_cap(adev->pdev);
6195+
}
6196+
}
6197+
61606198
/**
61616199
* amdgpu_device_get_pcie_info - fence pcie info about the PCIE slot
61626200
*
@@ -6168,9 +6206,8 @@ static void amdgpu_device_partner_bandwidth(struct amdgpu_device *adev,
61686206
*/
61696207
static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev)
61706208
{
6171-
struct pci_dev *pdev;
61726209
enum pci_bus_speed speed_cap, platform_speed_cap;
6173-
enum pcie_link_width platform_link_width;
6210+
enum pcie_link_width platform_link_width, link_width;
61746211

61756212
if (amdgpu_pcie_gen_cap)
61766213
adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap;
@@ -6192,11 +6229,10 @@ static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev)
61926229

61936230
amdgpu_device_partner_bandwidth(adev, &platform_speed_cap,
61946231
&platform_link_width);
6232+
amdgpu_device_gpu_bandwidth(adev, &speed_cap, &link_width);
61956233

61966234
if (adev->pm.pcie_gen_mask == 0) {
61976235
/* asic caps */
6198-
pdev = adev->pdev;
6199-
speed_cap = pcie_get_speed_cap(pdev);
62006236
if (speed_cap == PCI_SPEED_UNKNOWN) {
62016237
adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
62026238
CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
@@ -6252,51 +6288,103 @@ static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev)
62526288
}
62536289
}
62546290
if (adev->pm.pcie_mlw_mask == 0) {
6291+
/* asic caps */
6292+
if (link_width == PCIE_LNK_WIDTH_UNKNOWN) {
6293+
adev->pm.pcie_mlw_mask |= AMDGPU_DEFAULT_ASIC_PCIE_MLW_MASK;
6294+
} else {
6295+
switch (link_width) {
6296+
case PCIE_LNK_X32:
6297+
adev->pm.pcie_mlw_mask |= (CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X32 |
6298+
CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X16 |
6299+
CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X12 |
6300+
CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X8 |
6301+
CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X4 |
6302+
CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X2 |
6303+
CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X1);
6304+
break;
6305+
case PCIE_LNK_X16:
6306+
adev->pm.pcie_mlw_mask |= (CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X16 |
6307+
CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X12 |
6308+
CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X8 |
6309+
CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X4 |
6310+
CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X2 |
6311+
CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X1);
6312+
break;
6313+
case PCIE_LNK_X12:
6314+
adev->pm.pcie_mlw_mask |= (CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X12 |
6315+
CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X8 |
6316+
CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X4 |
6317+
CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X2 |
6318+
CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X1);
6319+
break;
6320+
case PCIE_LNK_X8:
6321+
adev->pm.pcie_mlw_mask |= (CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X8 |
6322+
CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X4 |
6323+
CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X2 |
6324+
CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X1);
6325+
break;
6326+
case PCIE_LNK_X4:
6327+
adev->pm.pcie_mlw_mask |= (CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X4 |
6328+
CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X2 |
6329+
CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X1);
6330+
break;
6331+
case PCIE_LNK_X2:
6332+
adev->pm.pcie_mlw_mask |= (CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X2 |
6333+
CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X1);
6334+
break;
6335+
case PCIE_LNK_X1:
6336+
adev->pm.pcie_mlw_mask |= CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X1;
6337+
break;
6338+
default:
6339+
break;
6340+
}
6341+
}
6342+
/* platform caps */
62556343
if (platform_link_width == PCIE_LNK_WIDTH_UNKNOWN) {
62566344
adev->pm.pcie_mlw_mask |= AMDGPU_DEFAULT_PCIE_MLW_MASK;
62576345
} else {
62586346
switch (platform_link_width) {
62596347
case PCIE_LNK_X32:
6260-
adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
6261-
CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
6262-
CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
6263-
CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
6264-
CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
6265-
CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
6266-
CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
6348+
adev->pm.pcie_mlw_mask |= (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
6349+
CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
6350+
CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
6351+
CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
6352+
CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
6353+
CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
6354+
CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
62676355
break;
62686356
case PCIE_LNK_X16:
6269-
adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
6270-
CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
6271-
CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
6272-
CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
6273-
CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
6274-
CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
6357+
adev->pm.pcie_mlw_mask |= (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
6358+
CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
6359+
CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
6360+
CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
6361+
CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
6362+
CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
62756363
break;
62766364
case PCIE_LNK_X12:
6277-
adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
6278-
CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
6279-
CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
6280-
CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
6281-
CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
6365+
adev->pm.pcie_mlw_mask |= (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
6366+
CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
6367+
CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
6368+
CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
6369+
CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
62826370
break;
62836371
case PCIE_LNK_X8:
6284-
adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
6285-
CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
6286-
CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
6287-
CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
6372+
adev->pm.pcie_mlw_mask |= (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
6373+
CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
6374+
CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
6375+
CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
62886376
break;
62896377
case PCIE_LNK_X4:
6290-
adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
6291-
CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
6292-
CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
6378+
adev->pm.pcie_mlw_mask |= (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
6379+
CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
6380+
CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
62936381
break;
62946382
case PCIE_LNK_X2:
6295-
adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
6296-
CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
6383+
adev->pm.pcie_mlw_mask |= (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
6384+
CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
62976385
break;
62986386
case PCIE_LNK_X1:
6299-
adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;
6387+
adev->pm.pcie_mlw_mask |= CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;
63006388
break;
63016389
default:
63026390
break;

‎drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c‎

Lines changed: 13 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -280,7 +280,7 @@ module_param_named(gartsize, amdgpu_gart_size, uint, 0600);
280280
/**
281281
* DOC: gttsize (int)
282282
* Restrict the size of GTT domain (for userspace use) in MiB for testing.
283-
* The default is -1 (Use 1/2 RAM, minimum value is 3GB).
283+
* The default is -1 (Use value specified by TTM).
284284
*/
285285
MODULE_PARM_DESC(gttsize, "Size of the GTT userspace domain in megabytes (-1 = auto)");
286286
module_param_named(gttsize, amdgpu_gtt_size, int, 0600);
@@ -399,7 +399,7 @@ module_param_named(runpm, amdgpu_runtime_pm, int, 0444);
399399
* the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device).
400400
*/
401401
MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))");
402-
module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444);
402+
module_param_named_unsafe(ip_block_mask, amdgpu_ip_block_mask, uint, 0444);
403403

404404
/**
405405
* DOC: bapm (int)
@@ -457,7 +457,7 @@ module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444);
457457
* Enable experimental hw support (1 = enable). The default is 0 (disabled).
458458
*/
459459
MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))");
460-
module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444);
460+
module_param_named_unsafe(exp_hw_support, amdgpu_exp_hw_support, int, 0444);
461461

462462
/**
463463
* DOC: dc (int)
@@ -568,14 +568,14 @@ module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444);
568568
* Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV).
569569
*/
570570
MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)");
571-
module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444);
571+
module_param_named_unsafe(gpu_recovery, amdgpu_gpu_recovery, int, 0444);
572572

573573
/**
574574
* DOC: emu_mode (int)
575575
* Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled).
576576
*/
577577
MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)");
578-
module_param_named(emu_mode, amdgpu_emu_mode, int, 0444);
578+
module_param_named_unsafe(emu_mode, amdgpu_emu_mode, int, 0444);
579579

580580
/**
581581
* DOC: ras_enable (int)
@@ -730,7 +730,7 @@ module_param_named(noretry, amdgpu_noretry, int, 0644);
730730
*/
731731
MODULE_PARM_DESC(force_asic_type,
732732
"A non negative value used to specify the asic type for all supported GPUs");
733-
module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444);
733+
module_param_named_unsafe(force_asic_type, amdgpu_force_asic_type, int, 0444);
734734

735735
/**
736736
* DOC: use_xgmi_p2p (int)
@@ -749,7 +749,7 @@ module_param_named(use_xgmi_p2p, amdgpu_use_xgmi_p2p, int, 0444);
749749
* assigns queues to HQDs.
750750
*/
751751
int sched_policy = KFD_SCHED_POLICY_HWS;
752-
module_param(sched_policy, int, 0444);
752+
module_param_unsafe(sched_policy, int, 0444);
753753
MODULE_PARM_DESC(sched_policy,
754754
"Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)");
755755

@@ -799,7 +799,7 @@ MODULE_PARM_DESC(send_sigterm,
799799
* Setting 1 enables halt on hang.
800800
*/
801801
int halt_if_hws_hang;
802-
module_param(halt_if_hws_hang, int, 0644);
802+
module_param_unsafe(halt_if_hws_hang, int, 0644);
803803
MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)");
804804

805805
/**
@@ -808,7 +808,7 @@ MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (defau
808808
* check says. Default value: false (rely on MEC2 firmware version check).
809809
*/
810810
bool hws_gws_support;
811-
module_param(hws_gws_support, bool, 0444);
811+
module_param_unsafe(hws_gws_support, bool, 0444);
812812
MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)");
813813

814814
/**
@@ -841,15 +841,15 @@ MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = defa
841841
*/
842842
int amdgpu_no_queue_eviction_on_vm_fault;
843843
MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)");
844-
module_param_named(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444);
844+
module_param_named_unsafe(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444);
845845
#endif
846846

847847
/**
848848
* DOC: mtype_local (int)
849849
*/
850850
int amdgpu_mtype_local;
851851
MODULE_PARM_DESC(mtype_local, "MTYPE for local memory (0 = MTYPE_RW (default), 1 = MTYPE_NC, 2 = MTYPE_CC)");
852-
module_param_named(mtype_local, amdgpu_mtype_local, int, 0444);
852+
module_param_named_unsafe(mtype_local, amdgpu_mtype_local, int, 0444);
853853

854854
/**
855855
* DOC: pcie_p2p (bool)
@@ -953,7 +953,7 @@ module_param_named(freesync_video, amdgpu_freesync_vid_mode, uint, 0444);
953953
* GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco)
954954
*/
955955
MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco)");
956-
module_param_named(reset_method, amdgpu_reset_method, int, 0644);
956+
module_param_named_unsafe(reset_method, amdgpu_reset_method, int, 0644);
957957

958958
/**
959959
* DOC: bad_page_threshold (int) Bad page threshold is specifies the
@@ -1049,7 +1049,7 @@ module_param_named(seamless, amdgpu_seamless, int, 0444);
10491049
* - 0x4: Disable GPU soft recovery, always do a full reset
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*/
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MODULE_PARM_DESC(debug_mask, "debug options for amdgpu, disabled by default");
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module_param_named(debug_mask, amdgpu_debug_mask, uint, 0444);
1052+
module_param_named_unsafe(debug_mask, amdgpu_debug_mask, uint, 0444);
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/**
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* DOC: agp (int)

‎drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -297,7 +297,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs,
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amdgpu_ring_patch_cond_exec(ring, cond_exec);
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ring->current_ctx = fence_ctx;
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if (vm && ring->funcs->emit_switch_buffer)
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if (job && ring->funcs->emit_switch_buffer)
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amdgpu_ring_emit_switch_buffer(ring);
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if (ring->funcs->emit_wave_limit &&

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