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plbossartvinodkoul
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soundwire: bus: extend base clock checks to 96 MHz
Starting with MeteorLake, the input frequency to the SoundWire IP can be 96MHz. The existing code is limited to 24MHz, change accordingly and move branch after the 32MHz case to avoid issues. While we're at it, reorder the frequencies by increasing order. Signed-off-by: Pierre-Louis Bossart <[email protected]> Reviewed-by: Rander Wang <[email protected]> Signed-off-by: Bard Liao <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
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drivers/soundwire/bus.c

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1312,18 +1312,18 @@ static int sdw_slave_set_frequency(struct sdw_slave *slave)
13121312
if (!(19200000 % mclk_freq)) {
13131313
mclk_freq = 19200000;
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base = SDW_SCP_BASE_CLOCK_19200000_HZ;
1315-
} else if (!(24000000 % mclk_freq)) {
1316-
mclk_freq = 24000000;
1317-
base = SDW_SCP_BASE_CLOCK_24000000_HZ;
1318-
} else if (!(24576000 % mclk_freq)) {
1319-
mclk_freq = 24576000;
1320-
base = SDW_SCP_BASE_CLOCK_24576000_HZ;
13211315
} else if (!(22579200 % mclk_freq)) {
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mclk_freq = 22579200;
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base = SDW_SCP_BASE_CLOCK_22579200_HZ;
1318+
} else if (!(24576000 % mclk_freq)) {
1319+
mclk_freq = 24576000;
1320+
base = SDW_SCP_BASE_CLOCK_24576000_HZ;
13241321
} else if (!(32000000 % mclk_freq)) {
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mclk_freq = 32000000;
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base = SDW_SCP_BASE_CLOCK_32000000_HZ;
1324+
} else if (!(96000000 % mclk_freq)) {
1325+
mclk_freq = 24000000;
1326+
base = SDW_SCP_BASE_CLOCK_24000000_HZ;
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} else {
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dev_err(&slave->dev,
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"Unsupported clock base, mclk %d\n",

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