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Merge tag 'drm-next-20221025' of git://linuxtv.org/pinchartl/media into drm-next
Xilinx ZynqMP DisplayPort bridge support Signed-off-by: Dave Airlie <[email protected]> From: Laurent Pinchart <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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Documentation/devicetree/bindings/display/xlnx/xlnx,zynqmp-dpsub.yaml

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@@ -117,6 +117,45 @@ properties:
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- const: dp-phy0
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- const: dp-phy1
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ports:
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$ref: /schemas/graph.yaml#/properties/ports
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description: |
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Connections to the programmable logic and the DisplayPort PHYs. Each port
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shall have a single endpoint.
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properties:
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port@0:
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$ref: /schemas/graph.yaml#/properties/port
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description: The live video input from the programmable logic
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port@1:
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$ref: /schemas/graph.yaml#/properties/port
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description: The live graphics input from the programmable logic
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port@2:
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$ref: /schemas/graph.yaml#/properties/port
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description: The live audio input from the programmable logic
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port@3:
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$ref: /schemas/graph.yaml#/properties/port
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description: The blended video output to the programmable logic
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port@4:
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$ref: /schemas/graph.yaml#/properties/port
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description: The mixed audio output to the programmable logic
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port@5:
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$ref: /schemas/graph.yaml#/properties/port
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description: The DisplayPort output
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required:
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- port@0
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- port@1
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- port@2
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- port@3
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- port@4
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- port@5
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required:
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- compatible
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- reg
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- dma-names
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- phys
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- phy-names
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- ports
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additionalProperties: false
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<&psgtr 0 PHY_TYPE_DP 1 3>;
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phy-names = "dp-phy0", "dp-phy1";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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};
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port@1 {
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reg = <1>;
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};
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port@2 {
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reg = <2>;
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};
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port@3 {
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reg = <3>;
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};
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port@4 {
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reg = <4>;
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};
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port@5 {
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reg = <5>;
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dpsub_dp_out: endpoint {
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remote-endpoint = <&dp_connector>;
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};
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};
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};
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};
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...

arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts

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#clock-cells = <0>;
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clock-frequency = <114285000>;
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};
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dpcon {
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compatible = "dp-connector";
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label = "P11";
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type = "full-size";
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port {
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dpcon_in: endpoint {
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remote-endpoint = <&dpsub_dp_out>;
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};
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};
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};
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};
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&can1 {
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phy-names = "dp-phy0", "dp-phy1";
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phys = <&psgtr 1 PHY_TYPE_DP 0 3>,
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<&psgtr 0 PHY_TYPE_DP 1 3>;
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ports {
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port@5 {
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dpsub_dp_out: endpoint {
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remote-endpoint = <&dpcon_in>;
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};
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};
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};
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};

arch/arm64/boot/dts/xilinx/zynqmp.dtsi

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<&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO1>,
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<&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO2>,
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<&zynqmp_dpdma ZYNQMP_DPDMA_GRAPHICS>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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};
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port@1 {
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reg = <1>;
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};
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port@2 {
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reg = <2>;
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};
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port@3 {
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reg = <3>;
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};
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port@4 {
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reg = <4>;
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};
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port@5 {
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reg = <5>;
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};
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};
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};
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};
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};

drivers/gpu/drm/xlnx/Makefile

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zynqmp-dpsub-y := zynqmp_disp.o zynqmp_dpsub.o zynqmp_dp.o
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zynqmp-dpsub-y := zynqmp_disp.o zynqmp_dpsub.o zynqmp_dp.o zynqmp_kms.o
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obj-$(CONFIG_DRM_ZYNQMP_DPSUB) += zynqmp-dpsub.o

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