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5 | 5 | * Copyright (C) 2006 - 2009 Paul Mundt
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6 | 6 | * Copyright (C) 2006 Jamie Lenehan
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7 | 7 | * Copyright (C) 2008 Angelo Castello
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| 8 | + * Copyright (C) 2025 Wolfram Sang, Renesas Electronics Corporation |
8 | 9 | *
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9 | 10 | * Based on the old arch/sh/kernel/cpu/rtc.c by:
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10 | 11 | *
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31 | 32 | /* Default values for RZ/A RTC */
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32 | 33 | #define rtc_reg_size sizeof(u16)
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33 | 34 | #define RTC_BIT_INVERTED 0 /* no chip bugs */
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34 |
| -#define RTC_CAP_4_DIGIT_YEAR (1 << 0) |
| 35 | +#define RTC_CAP_4_DIGIT_YEAR BIT(0) |
35 | 36 | #define RTC_DEF_CAPABILITIES RTC_CAP_4_DIGIT_YEAR
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36 | 37 | #endif
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37 | 38 |
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70 | 71 | */
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71 | 72 |
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72 | 73 | /* ALARM Bits - or with BCD encoded value */
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73 |
| -#define AR_ENB 0x80 /* Enable for alarm cmp */ |
| 74 | +#define AR_ENB BIT(7) /* Enable for alarm cmp */ |
74 | 75 |
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75 | 76 | /* RCR1 Bits */
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76 |
| -#define RCR1_CF 0x80 /* Carry Flag */ |
77 |
| -#define RCR1_CIE 0x10 /* Carry Interrupt Enable */ |
78 |
| -#define RCR1_AIE 0x08 /* Alarm Interrupt Enable */ |
79 |
| -#define RCR1_AF 0x01 /* Alarm Flag */ |
| 77 | +#define RCR1_CF BIT(7) /* Carry Flag */ |
| 78 | +#define RCR1_CIE BIT(4) /* Carry Interrupt Enable */ |
| 79 | +#define RCR1_AIE BIT(3) /* Alarm Interrupt Enable */ |
| 80 | +#define RCR1_AF BIT(0) /* Alarm Flag */ |
80 | 81 |
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81 | 82 | /* RCR2 Bits */
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82 |
| -#define RCR2_RTCEN 0x08 /* ENable RTC */ |
83 |
| -#define RCR2_ADJ 0x04 /* ADJustment (30-second) */ |
84 |
| -#define RCR2_RESET 0x02 /* Reset bit */ |
85 |
| -#define RCR2_START 0x01 /* Start bit */ |
| 83 | +#define RCR2_RTCEN BIT(3) /* ENable RTC */ |
| 84 | +#define RCR2_ADJ BIT(2) /* ADJustment (30-second) */ |
| 85 | +#define RCR2_RESET BIT(1) /* Reset bit */ |
| 86 | +#define RCR2_START BIT(0) /* Start bit */ |
86 | 87 |
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87 | 88 | struct sh_rtc {
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88 | 89 | void __iomem *regbase;
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89 | 90 | int alarm_irq;
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90 | 91 | struct clk *clk;
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91 | 92 | struct rtc_device *rtc_dev;
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92 |
| - spinlock_t lock; |
| 93 | + spinlock_t lock; /* protecting register access */ |
93 | 94 | unsigned long capabilities; /* See asm/rtc.h for cap bits */
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94 | 95 | };
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95 | 96 |
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@@ -183,10 +184,8 @@ static int sh_rtc_read_time(struct device *dev, struct rtc_time *tm)
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183 | 184 | tm->tm_sec--;
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184 | 185 | #endif
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185 | 186 |
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186 |
| - dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, " |
187 |
| - "mday=%d, mon=%d, year=%d, wday=%d\n", |
188 |
| - __func__, |
189 |
| - tm->tm_sec, tm->tm_min, tm->tm_hour, |
| 187 | + dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n", |
| 188 | + __func__, tm->tm_sec, tm->tm_min, tm->tm_hour, |
190 | 189 | tm->tm_mday, tm->tm_mon + 1, tm->tm_year, tm->tm_wday);
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191 | 190 |
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192 | 191 | return 0;
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@@ -373,8 +372,9 @@ static int __init sh_rtc_probe(struct platform_device *pdev)
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373 | 372 | clk_id = 0;
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374 | 373 |
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375 | 374 | snprintf(clk_name, sizeof(clk_name), "rtc%d", clk_id);
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376 |
| - } else |
| 375 | + } else { |
377 | 376 | snprintf(clk_name, sizeof(clk_name), "fck");
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| 377 | + } |
378 | 378 |
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379 | 379 | rtc->clk = devm_clk_get(&pdev->dev, clk_name);
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380 | 380 | if (IS_ERR(rtc->clk)) {
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@@ -501,8 +501,8 @@ static struct platform_driver sh_rtc_platform_driver __refdata = {
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501 | 501 | module_platform_driver_probe(sh_rtc_platform_driver, sh_rtc_probe);
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502 | 502 |
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503 | 503 | MODULE_DESCRIPTION("SuperH on-chip RTC driver");
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504 |
| -MODULE_AUTHOR( "Paul Mundt <[email protected]>, " |
505 |
| - "Jamie Lenehan <[email protected]>, " |
506 |
| - "Angelo Castello <[email protected]>"); |
| 504 | +MODULE_AUTHOR( "Paul Mundt <[email protected]>"); |
| 505 | +MODULE_AUTHOR("Jamie Lenehan <[email protected]>"); |
| 506 | +MODULE_AUTHOR("Angelo Castello <[email protected]>"); |
507 | 507 | MODULE_LICENSE("GPL v2");
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508 | 508 | MODULE_ALIAS("platform:" DRV_NAME);
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