drm/amd/powerplay: fix pre-check condition for setting clock range

Prike Liang · alexdeucher · commit 80381d40c9bf · 2020-03-05T09:42:08.000-05:00
This fix will handle some MP1 FW issue like as mclk dpm table in renoir has a reverse
dpm clock layout and a zero frequency dpm level as following case.

cat pp_dpm_mclk
0: 1200Mhz
1: 1200Mhz
2: 800Mhz
3: 0Mhz

Signed-off-by: Prike Liang &lt;Prike.Liang@amd.com&gt;
Reviewed-by: Evan Quan &lt;evan.quan@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -222,7 +222,7 @@ int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
 {
 	int ret = 0;
 
-	if (min <= 0 && max <= 0)
+	if (min < 0 && max < 0)
 		return -EINVAL;
 
 	if (!smu_clk_dpm_is_enabled(smu, clk_type))
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
@@ -458,9 +458,6 @@ int smu_v12_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_
 {
 	int ret = 0;
 
-	if (max < min)
-		return -EINVAL;
-
 	switch (clk_type) {
 	case SMU_GFXCLK:
 	case SMU_SCLK:

Original file line number	Diff line number	Diff line change
`@@ -222,7 +222,7 @@ int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,`
`222`	`222`	`{`
`223`	`223`	`int ret = 0;`
`224`	`224`
`225`		`- if (min <= 0 && max <= 0)`
	`225`	`+ if (min < 0 && max < 0)`
`226`	`226`	`return -EINVAL;`
`227`	`227`
`228`	`228`	`if (!smu_clk_dpm_is_enabled(smu, clk_type))`
Original file line number	Diff line number	Diff line change
`@@ -458,9 +458,6 @@ int smu_v12_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_`
`458`	`458`	`{`
`459`	`459`	`int ret = 0;`
`460`	`460`
`461`		`- if (max < min)`
`462`		`- return -EINVAL;`
`463`		`-`
`464`	`461`	`switch (clk_type) {`
`465`	`462`	`case SMU_GFXCLK:`
`466`	`463`	`case SMU_SCLK:`