Skip to content

Commit 8053d2f

Browse files
torvaldstorvalds
committed
Merge tag 'phy-for-6.10' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy
Pull generic phy updates from Vinod Koul: "New HW Support: - Support for Embedded DisplayPort and DisplayPort submodes and driver support on Qualcomm X1E80100 edp driver - Qualcomm QMP UFS PHY for SM8475, QMP USB phy for QDU1000/QRU1000 and eusb2-repeater for SMB2360 - Samsung HDMI PHY for i.MX8MP, gs101 UFS phy - Mediatek XFI T-PHY support for mt7988 - Rockchip usbdp combo phy driver Updates: - Qualcomm x4 lane EP support for sa8775p, v4 ad v6 support for X1E80100, SM8650 tables for UFS Gear 4 & 5 and correct voltage swing tables - Freescale imx8m-pci pcie link-up updates - Rockchip rx-common-refclk-mode support - More platform remove callback returning void conversions" * tag 'phy-for-6.10' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (43 commits) dt-bindings: phy: qcom,usb-snps-femto-v2: use correct fallback for sc8180x dt-bindings: phy: qcom,sc8280xp-qmp-ufs-phy: fix msm899[68] power-domains dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: fix x1e80100-gen3x2 schema phy: qcpm-qmp-usb: Add support for QDU1000/QRU1000 dt-bindings: phy: qcom,qmp-usb: Add QDU1000 USB3 PHY dt-bindings: phy: qcom,usb-snps-femto-v2: Add bindings for QDU1000 phy: qcom-qmp-pcie: add x4 lane EP support for sa8775p phy: samsung-ufs: ufs: exit on first reported error phy: samsung-ufs: ufs: remove superfluous mfd/syscon.h header phy: rockchip: fix CONFIG_TYPEC dependency phy: rockchip: usbdp: fix uninitialized variable phy: rockchip-snps-pcie3: add support for rockchip,rx-common-refclk-mode dt-bindings: phy: rockchip,pcie3-phy: add rockchip,rx-common-refclk-mode phy: rockchip: add usbdp combo phy driver dt-bindings: phy: add rockchip usbdp combo phy document phy: add driver for MediaTek XFI T-PHY dt-bindings: phy: mediatek,mt7988-xfi-tphy: add new bindings phy: freescale: fsl-samsung-hdmi: Convert to platform remove callback returning void phy: qcom: qmp-ufs: update SM8650 tables for Gear 4 & 5 MAINTAINERS: Add phy-gs101-ufs file to Tensor GS101. ...
2 parents d4e034b + 960b3f0 commit 8053d2f

Some content is hidden

Large Commits have some content hidden by default. Use the searchbox below for content that may be hidden.

41 files changed

+4076
-106
lines changed

‎Documentation/devicetree/bindings/phy/fsl,imx8mp-hdmi-phy.yaml

Lines changed: 62 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,62 @@
1+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+
%YAML 1.2
3+
---
4+
$id: http://devicetree.org/schemas/phy/fsl,imx8mp-hdmi-phy.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: Freescale i.MX8MP HDMI PHY
8+
9+
maintainers:
10+
- Lucas Stach <[email protected]>
11+
12+
properties:
13+
compatible:
14+
enum:
15+
- fsl,imx8mp-hdmi-phy
16+
17+
reg:
18+
maxItems: 1
19+
20+
"#clock-cells":
21+
const: 0
22+
23+
clocks:
24+
maxItems: 2
25+
26+
clock-names:
27+
items:
28+
- const: apb
29+
- const: ref
30+
31+
"#phy-cells":
32+
const: 0
33+
34+
power-domains:
35+
maxItems: 1
36+
37+
required:
38+
- compatible
39+
- reg
40+
- "#clock-cells"
41+
- clocks
42+
- clock-names
43+
- "#phy-cells"
44+
- power-domains
45+
46+
additionalProperties: false
47+
48+
examples:
49+
- |
50+
#include <dt-bindings/clock/imx8mp-clock.h>
51+
#include <dt-bindings/power/imx8mp-power.h>
52+
53+
phy@32fdff00 {
54+
compatible = "fsl,imx8mp-hdmi-phy";
55+
reg = <0x32fdff00 0x100>;
56+
clocks = <&clk IMX8MP_CLK_HDMI_APB>,
57+
<&clk IMX8MP_CLK_HDMI_24M>;
58+
clock-names = "apb", "ref";
59+
power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX_PHY>;
60+
#clock-cells = <0>;
61+
#phy-cells = <0>;
62+
};

‎Documentation/devicetree/bindings/phy/mediatek,mt7988-xfi-tphy.yaml

Lines changed: 80 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,80 @@
1+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+
%YAML 1.2
3+
---
4+
$id: http://devicetree.org/schemas/phy/mediatek,mt7988-xfi-tphy.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: MediaTek MT7988 XFI T-PHY
8+
9+
maintainers:
10+
- Daniel Golle <[email protected]>
11+
12+
description:
13+
The MediaTek XFI SerDes T-PHY provides the physical SerDes lanes
14+
used by the (10G/5G) USXGMII PCS and (1G/2.5G) LynxI PCS found in
15+
MediaTek's 10G-capabale MT7988 SoC.
16+
In MediaTek's SDK sources, this unit is referred to as "pextp".
17+
18+
properties:
19+
compatible:
20+
const: mediatek,mt7988-xfi-tphy
21+
22+
reg:
23+
maxItems: 1
24+
25+
clocks:
26+
items:
27+
- description: XFI PHY clock
28+
- description: XFI register clock
29+
30+
clock-names:
31+
items:
32+
- const: xfipll
33+
- const: topxtal
34+
35+
resets:
36+
items:
37+
- description: Reset controller corresponding to the phy instance.
38+
39+
mediatek,usxgmii-performance-errata:
40+
$ref: /schemas/types.yaml#/definitions/flag
41+
description:
42+
One instance of the T-PHY on MT7988 suffers from a performance
43+
problem in 10GBase-R mode which needs a work-around in the driver.
44+
This flag enables a work-around ajusting an analog phy setting and
45+
is required for XFI Port0 of the MT7988 SoC to be in compliance with
46+
the SFP specification.
47+
48+
"#phy-cells":
49+
const: 0
50+
51+
required:
52+
- compatible
53+
- reg
54+
- clocks
55+
- clock-names
56+
- resets
57+
- "#phy-cells"
58+
59+
additionalProperties: false
60+
61+
examples:
62+
- |
63+
#include <dt-bindings/clock/mediatek,mt7988-clk.h>
64+
soc {
65+
#address-cells = <2>;
66+
#size-cells = <2>;
67+
68+
phy@11f20000 {
69+
compatible = "mediatek,mt7988-xfi-tphy";
70+
reg = <0 0x11f20000 0 0x10000>;
71+
clocks = <&xfi_pll CLK_XFIPLL_PLL_EN>,
72+
<&topckgen CLK_TOP_XFI_PHY_0_XTAL_SEL>;
73+
clock-names = "xfipll", "topxtal";
74+
resets = <&watchdog 14>;
75+
mediatek,usxgmii-performance-errata;
76+
#phy-cells = <0>;
77+
};
78+
};
79+
80+
...

‎Documentation/devicetree/bindings/phy/phy-rockchip-usbdp.yaml

Lines changed: 148 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,148 @@
1+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+
%YAML 1.2
3+
---
4+
$id: http://devicetree.org/schemas/phy/phy-rockchip-usbdp.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: Rockchip USBDP Combo PHY with Samsung IP block
8+
9+
maintainers:
10+
- Frank Wang <[email protected]>
11+
- Zhang Yubing <[email protected]>
12+
13+
properties:
14+
compatible:
15+
enum:
16+
- rockchip,rk3588-usbdp-phy
17+
18+
reg:
19+
maxItems: 1
20+
21+
"#phy-cells":
22+
description: |
23+
Cell allows setting the type of the PHY. Possible values are:
24+
- PHY_TYPE_USB3
25+
- PHY_TYPE_DP
26+
const: 1
27+
28+
clocks:
29+
maxItems: 4
30+
31+
clock-names:
32+
items:
33+
- const: refclk
34+
- const: immortal
35+
- const: pclk
36+
- const: utmi
37+
38+
resets:
39+
maxItems: 5
40+
41+
reset-names:
42+
items:
43+
- const: init
44+
- const: cmn
45+
- const: lane
46+
- const: pcs_apb
47+
- const: pma_apb
48+
49+
rockchip,dp-lane-mux:
50+
$ref: /schemas/types.yaml#/definitions/uint32-array
51+
minItems: 2
52+
maxItems: 4
53+
items:
54+
maximum: 3
55+
description:
56+
An array of physical Type-C lanes indexes. Position of an entry
57+
determines the DisplayPort (DP) lane index, while the value of an entry
58+
indicates physical Type-C lane. The supported DP lanes number are 2 or 4.
59+
e.g. for 2 lanes DP lanes map, we could have "rockchip,dp-lane-mux = <2,
60+
3>;", assuming DP lane0 on Type-C phy lane2, DP lane1 on Type-C phy
61+
lane3. For 4 lanes DP lanes map, we could have "rockchip,dp-lane-mux =
62+
<0, 1, 2, 3>;", assuming DP lane0 on Type-C phy lane0, DP lane1 on Type-C
63+
phy lane1, DP lane2 on Type-C phy lane2, DP lane3 on Type-C phy lane3. If
64+
DP lanes are mapped by DisplayPort Alt mode, this property is not needed.
65+
66+
rockchip,u2phy-grf:
67+
$ref: /schemas/types.yaml#/definitions/phandle
68+
description:
69+
Phandle to the syscon managing the 'usb2 phy general register files'.
70+
71+
rockchip,usb-grf:
72+
$ref: /schemas/types.yaml#/definitions/phandle
73+
description:
74+
Phandle to the syscon managing the 'usb general register files'.
75+
76+
rockchip,usbdpphy-grf:
77+
$ref: /schemas/types.yaml#/definitions/phandle
78+
description:
79+
Phandle to the syscon managing the 'usbdp phy general register files'.
80+
81+
rockchip,vo-grf:
82+
$ref: /schemas/types.yaml#/definitions/phandle
83+
description:
84+
Phandle to the syscon managing the 'video output general register files'.
85+
When select the DP lane mapping will request its phandle.
86+
87+
sbu1-dc-gpios:
88+
description:
89+
GPIO connected to the SBU1 line of the USB-C connector via a big resistor
90+
(~100K) to apply a DC offset for signalling the connector orientation.
91+
maxItems: 1
92+
93+
sbu2-dc-gpios:
94+
description:
95+
GPIO connected to the SBU2 line of the USB-C connector via a big resistor
96+
(~100K) to apply a DC offset for signalling the connector orientation.
97+
maxItems: 1
98+
99+
orientation-switch:
100+
description: Flag the port as possible handler of orientation switching
101+
type: boolean
102+
103+
mode-switch:
104+
description: Flag the port as possible handler of altmode switching
105+
type: boolean
106+
107+
port:
108+
$ref: /schemas/graph.yaml#/properties/port
109+
description:
110+
A port node to link the PHY to a TypeC controller for the purpose of
111+
handling orientation switching.
112+
113+
required:
114+
- compatible
115+
- reg
116+
- clocks
117+
- clock-names
118+
- resets
119+
- reset-names
120+
- "#phy-cells"
121+
122+
additionalProperties: false
123+
124+
examples:
125+
- |
126+
#include <dt-bindings/clock/rockchip,rk3588-cru.h>
127+
#include <dt-bindings/reset/rockchip,rk3588-cru.h>
128+
129+
usbdp_phy0: phy@fed80000 {
130+
compatible = "rockchip,rk3588-usbdp-phy";
131+
reg = <0xfed80000 0x10000>;
132+
#phy-cells = <1>;
133+
clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
134+
<&cru CLK_USBDP_PHY0_IMMORTAL>,
135+
<&cru PCLK_USBDPPHY0>,
136+
<&u2phy0>;
137+
clock-names = "refclk", "immortal", "pclk", "utmi";
138+
resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>,
139+
<&cru SRST_USBDP_COMBO_PHY0_CMN>,
140+
<&cru SRST_USBDP_COMBO_PHY0_LANE>,
141+
<&cru SRST_USBDP_COMBO_PHY0_PCS>,
142+
<&cru SRST_P_USBDPPHY0>;
143+
reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
144+
rockchip,u2phy-grf = <&usb2phy0_grf>;
145+
rockchip,usb-grf = <&usb_grf>;
146+
rockchip,usbdpphy-grf = <&usbdpphy0_grf>;
147+
rockchip,vo-grf = <&vo0_grf>;
148+
};

‎Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -21,6 +21,7 @@ properties:
2121
- qcom,sc8180x-edp-phy
2222
- qcom,sc8280xp-dp-phy
2323
- qcom,sc8280xp-edp-phy
24+
- qcom,x1e80100-dp-phy
2425

2526
reg:
2627
items:

‎Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml

Lines changed: 24 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -88,11 +88,11 @@ properties:
8888
- description: offset of PCIe 4-lane configuration register
8989
- description: offset of configuration bit for this PHY
9090

91-
"#clock-cells":
92-
const: 0
91+
"#clock-cells": true
9392

9493
clock-output-names:
95-
maxItems: 1
94+
minItems: 1
95+
maxItems: 2
9696

9797
"#phy-cells":
9898
const: 0
@@ -198,7 +198,6 @@ allOf:
198198
enum:
199199
- qcom,sm8550-qmp-gen4x2-pcie-phy
200200
- qcom,sm8650-qmp-gen4x2-pcie-phy
201-
- qcom,x1e80100-qmp-gen3x2-pcie-phy
202201
- qcom,x1e80100-qmp-gen4x2-pcie-phy
203202
then:
204203
properties:
@@ -213,6 +212,27 @@ allOf:
213212
reset-names:
214213
maxItems: 1
215214

215+
- if:
216+
properties:
217+
compatible:
218+
contains:
219+
enum:
220+
- qcom,sm8450-qmp-gen4x2-pcie-phy
221+
- qcom,sm8550-qmp-gen4x2-pcie-phy
222+
- qcom,sm8650-qmp-gen4x2-pcie-phy
223+
then:
224+
properties:
225+
clock-output-names:
226+
minItems: 2
227+
"#clock-cells":
228+
const: 1
229+
else:
230+
properties:
231+
clock-output-names:
232+
maxItems: 1
233+
"#clock-cells":
234+
const: 0
235+
216236
examples:
217237
- |
218238
#include <dt-bindings/clock/qcom,gcc-sc8280xp.h>

0 commit comments

Comments
 (0)