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Merge tag 'v6.15-rockchip-dtsfixes1' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/fixes
Removal of operating-points above what the rk3588j soc is rated for, and a number of smaller fixes: Turing RK1 fan can spin down again, fixed pins, pinmuxing and clocks and some devicetree-correctnes improvements. * tag 'v6.15-rockchip-dtsfixes1' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: arm64: dts: rockchip: fix Sige5 RTC interrupt pin arm64: dts: rockchip: Assign RT5616 MCLK rate on rk3588-friendlyelec-cm3588 arm64: dts: rockchip: Align wifi node name with bindings in CB2 arm64: dts: rockchip: Fix mmc-pwrseq clock name on rock-pi-4 arm64: dts: rockchip: Use "regulator-fixed" for btreg on px30-engicam for vcc3v3-btreg arm64: dts: rockchip: Add pinmuxing for eMMC on QNAP TS433 arm64: dts: rockchip: Remove overdrive-mode OPPs from RK3588J SoC dtsi arm64: dts: rockchip: Allow Turing RK1 cooling fan to spin down Link: https://lore.kernel.org/r/2923598.88bMQJbFj6@diego Signed-off-by: Arnd Bergmann <[email protected]>
2 parents 2ef5c66 + 4bf593b commit 81b7cf8

10 files changed

+31
-43
lines changed

‎arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -31,15 +31,14 @@
3131
};
3232

3333
vcc3v3_btreg: vcc3v3-btreg {
34-
compatible = "regulator-gpio";
34+
compatible = "regulator-fixed";
3535
enable-active-high;
3636
pinctrl-names = "default";
3737
pinctrl-0 = <&bt_enable_h>;
3838
regulator-name = "btreg-gpio-supply";
3939
regulator-min-microvolt = <3300000>;
4040
regulator-max-microvolt = <3300000>;
4141
regulator-always-on;
42-
states = <3300000 0x0>;
4342
};
4443

4544
vcc3v3_rf_aux_mod: regulator-vcc3v3-rf-aux-mod {

‎arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -26,5 +26,5 @@
2626
};
2727

2828
&vcc3v3_btreg {
29-
enable-gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>;
29+
gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>;
3030
};

‎arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -39,5 +39,5 @@
3939
};
4040

4141
&vcc3v3_btreg {
42-
enable-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>;
42+
gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>;
4343
};

‎arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -43,7 +43,7 @@
4343
sdio_pwrseq: sdio-pwrseq {
4444
compatible = "mmc-pwrseq-simple";
4545
clocks = <&rk808 1>;
46-
clock-names = "lpo";
46+
clock-names = "ext_clock";
4747
pinctrl-names = "default";
4848
pinctrl-0 = <&wifi_enable_h>;
4949
reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;

‎arch/arm64/boot/dts/rockchip/rk3566-bigtreetech-cb2.dtsi

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -775,7 +775,7 @@
775775
rockchip,default-sample-phase = <90>;
776776
status = "okay";
777777

778-
sdio-wifi@1 {
778+
wifi@1 {
779779
compatible = "brcm,bcm4329-fmac";
780780
reg = <1>;
781781
interrupt-parent = <&gpio2>;

‎arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433.dts

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -619,6 +619,8 @@
619619
bus-width = <8>;
620620
max-frequency = <200000000>;
621621
non-removable;
622+
pinctrl-names = "default";
623+
pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
622624
status = "okay";
623625
};
624626

‎arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -610,7 +610,7 @@
610610
reg = <0x51>;
611611
clock-output-names = "hym8563";
612612
interrupt-parent = <&gpio0>;
613-
interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
613+
interrupts = <RK_PA0 IRQ_TYPE_LEVEL_LOW>;
614614
pinctrl-names = "default";
615615
pinctrl-0 = <&hym8563_int>;
616616
wakeup-source;

‎arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588.dtsi

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -222,6 +222,10 @@
222222
compatible = "realtek,rt5616";
223223
reg = <0x1b>;
224224
#sound-dai-cells = <0>;
225+
assigned-clocks = <&cru I2S0_8CH_MCLKOUT>;
226+
assigned-clock-rates = <12288000>;
227+
clocks = <&cru I2S0_8CH_MCLKOUT>;
228+
clock-names = "mclk";
225229
};
226230
};
227231

‎arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -214,6 +214,8 @@
214214
};
215215

216216
&package_thermal {
217+
polling-delay = <1000>;
218+
217219
trips {
218220
package_active1: trip-active1 {
219221
temperature = <45000>;

‎arch/arm64/boot/dts/rockchip/rk3588j.dtsi

Lines changed: 17 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -11,20 +11,15 @@
1111
compatible = "operating-points-v2";
1212
opp-shared;
1313

14-
opp-1416000000 {
15-
opp-hz = /bits/ 64 <1416000000>;
14+
opp-1200000000 {
15+
opp-hz = /bits/ 64 <1200000000>;
1616
opp-microvolt = <750000 750000 950000>;
1717
clock-latency-ns = <40000>;
1818
opp-suspend;
1919
};
20-
opp-1608000000 {
21-
opp-hz = /bits/ 64 <1608000000>;
22-
opp-microvolt = <887500 887500 950000>;
23-
clock-latency-ns = <40000>;
24-
};
25-
opp-1704000000 {
26-
opp-hz = /bits/ 64 <1704000000>;
27-
opp-microvolt = <937500 937500 950000>;
20+
opp-1296000000 {
21+
opp-hz = /bits/ 64 <1296000000>;
22+
opp-microvolt = <775000 775000 950000>;
2823
clock-latency-ns = <40000>;
2924
};
3025
};
@@ -33,52 +28,42 @@
3328
compatible = "operating-points-v2";
3429
opp-shared;
3530

31+
opp-1200000000{
32+
opp-hz = /bits/ 64 <1200000000>;
33+
opp-microvolt = <750000 750000 950000>;
34+
clock-latency-ns = <40000>;
35+
};
3636
opp-1416000000 {
3737
opp-hz = /bits/ 64 <1416000000>;
38-
opp-microvolt = <750000 750000 950000>;
38+
opp-microvolt = <762500 762500 950000>;
3939
clock-latency-ns = <40000>;
4040
};
4141
opp-1608000000 {
4242
opp-hz = /bits/ 64 <1608000000>;
4343
opp-microvolt = <787500 787500 950000>;
4444
clock-latency-ns = <40000>;
4545
};
46-
opp-1800000000 {
47-
opp-hz = /bits/ 64 <1800000000>;
48-
opp-microvolt = <875000 875000 950000>;
49-
clock-latency-ns = <40000>;
50-
};
51-
opp-2016000000 {
52-
opp-hz = /bits/ 64 <2016000000>;
53-
opp-microvolt = <950000 950000 950000>;
54-
clock-latency-ns = <40000>;
55-
};
5646
};
5747

5848
cluster2_opp_table: opp-table-cluster2 {
5949
compatible = "operating-points-v2";
6050
opp-shared;
6151

52+
opp-1200000000{
53+
opp-hz = /bits/ 64 <1200000000>;
54+
opp-microvolt = <750000 750000 950000>;
55+
clock-latency-ns = <40000>;
56+
};
6257
opp-1416000000 {
6358
opp-hz = /bits/ 64 <1416000000>;
64-
opp-microvolt = <750000 750000 950000>;
59+
opp-microvolt = <762500 762500 950000>;
6560
clock-latency-ns = <40000>;
6661
};
6762
opp-1608000000 {
6863
opp-hz = /bits/ 64 <1608000000>;
6964
opp-microvolt = <787500 787500 950000>;
7065
clock-latency-ns = <40000>;
7166
};
72-
opp-1800000000 {
73-
opp-hz = /bits/ 64 <1800000000>;
74-
opp-microvolt = <875000 875000 950000>;
75-
clock-latency-ns = <40000>;
76-
};
77-
opp-2016000000 {
78-
opp-hz = /bits/ 64 <2016000000>;
79-
opp-microvolt = <950000 950000 950000>;
80-
clock-latency-ns = <40000>;
81-
};
8267
};
8368

8469
gpu_opp_table: opp-table {
@@ -104,10 +89,6 @@
10489
opp-hz = /bits/ 64 <700000000>;
10590
opp-microvolt = <750000 750000 850000>;
10691
};
107-
opp-850000000 {
108-
opp-hz = /bits/ 64 <800000000>;
109-
opp-microvolt = <787500 787500 850000>;
110-
};
11192
};
11293
};
11394

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