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drm/i915/dpio: Clean up bxt/glk PHY registers
Use REG_BIT() & co. for the bxt/glk PHY register definitons. Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Jani Nikula <[email protected]>
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-59
lines changed

2 files changed

+59
-59
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‎drivers/gpu/drm/i915/display/intel_dpio_phy.c

Lines changed: 22 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -295,9 +295,9 @@ void bxt_ddi_phy_set_signal_levels(struct intel_encoder *encoder,
295295
intel_de_write(dev_priv, BXT_PORT_PCS_DW10_GRP(phy, ch), val);
296296

297297
val = intel_de_read(dev_priv, BXT_PORT_TX_DW2_LN0(phy, ch));
298-
val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE);
299-
val |= trans->entries[level].bxt.margin << MARGIN_000_SHIFT |
300-
trans->entries[level].bxt.scale << UNIQ_TRANS_SCALE_SHIFT;
298+
val &= ~(MARGIN_000_MASK | UNIQ_TRANS_SCALE_MASK);
299+
val |= MARGIN_000(trans->entries[level].bxt.margin) |
300+
UNIQ_TRANS_SCALE(trans->entries[level].bxt.scale);
301301
intel_de_write(dev_priv, BXT_PORT_TX_DW2_GRP(phy, ch), val);
302302

303303
val = intel_de_read(dev_priv, BXT_PORT_TX_DW3_LN0(phy, ch));
@@ -312,8 +312,8 @@ void bxt_ddi_phy_set_signal_levels(struct intel_encoder *encoder,
312312
intel_de_write(dev_priv, BXT_PORT_TX_DW3_GRP(phy, ch), val);
313313

314314
val = intel_de_read(dev_priv, BXT_PORT_TX_DW4_LN0(phy, ch));
315-
val &= ~DE_EMPHASIS;
316-
val |= trans->entries[level].bxt.deemphasis << DEEMPH_SHIFT;
315+
val &= ~DE_EMPHASIS_MASK;
316+
val |= DE_EMPHASIS(trans->entries[level].bxt.deemphasis);
317317
intel_de_write(dev_priv, BXT_PORT_TX_DW4_GRP(phy, ch), val);
318318

319319
val = intel_de_read(dev_priv, BXT_PORT_PCS_DW10_LN01(phy, ch));
@@ -353,7 +353,7 @@ static u32 bxt_get_grc(struct drm_i915_private *dev_priv, enum dpio_phy phy)
353353
{
354354
u32 val = intel_de_read(dev_priv, BXT_PORT_REF_DW6(phy));
355355

356-
return (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT;
356+
return REG_FIELD_GET(GRC_CODE_MASK, val);
357357
}
358358

359359
static void bxt_phy_wait_grc_done(struct drm_i915_private *dev_priv,
@@ -405,11 +405,11 @@ static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv,
405405
phy);
406406

407407
/* Program PLL Rcomp code offset */
408-
intel_de_rmw(dev_priv, BXT_PORT_CL1CM_DW9(phy), IREF0RC_OFFSET_MASK,
409-
0xE4 << IREF0RC_OFFSET_SHIFT);
408+
intel_de_rmw(dev_priv, BXT_PORT_CL1CM_DW9(phy),
409+
IREF0RC_OFFSET_MASK, IREF0RC_OFFSET(0xE4));
410410

411-
intel_de_rmw(dev_priv, BXT_PORT_CL1CM_DW10(phy), IREF1RC_OFFSET_MASK,
412-
0xE4 << IREF1RC_OFFSET_SHIFT);
411+
intel_de_rmw(dev_priv, BXT_PORT_CL1CM_DW10(phy),
412+
IREF1RC_OFFSET_MASK, IREF1RC_OFFSET(0xE4));
413413

414414
/* Program power gating */
415415
intel_de_rmw(dev_priv, BXT_PORT_CL1CM_DW28(phy), 0,
@@ -432,9 +432,9 @@ static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv,
432432
val = bxt_get_grc(dev_priv, phy_info->rcomp_phy);
433433
dev_priv->display.state.bxt_phy_grc = val;
434434

435-
grc_code = val << GRC_CODE_FAST_SHIFT |
436-
val << GRC_CODE_SLOW_SHIFT |
437-
val;
435+
grc_code = GRC_CODE_FAST(val) |
436+
GRC_CODE_SLOW(val) |
437+
GRC_CODE_NOM(val);
438438
intel_de_write(dev_priv, BXT_PORT_REF_DW6(phy), grc_code);
439439
intel_de_rmw(dev_priv, BXT_PORT_REF_DW8(phy),
440440
0, GRC_DIS | GRC_RDY_OVRD);
@@ -530,16 +530,16 @@ bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
530530

531531
/* PLL Rcomp code offset */
532532
ok &= _CHK(BXT_PORT_CL1CM_DW9(phy),
533-
IREF0RC_OFFSET_MASK, 0xe4 << IREF0RC_OFFSET_SHIFT,
534-
"BXT_PORT_CL1CM_DW9(%d)", phy);
533+
IREF0RC_OFFSET_MASK, IREF0RC_OFFSET(0xe4),
534+
"BXT_PORT_CL1CM_DW9(%d)", phy);
535535
ok &= _CHK(BXT_PORT_CL1CM_DW10(phy),
536-
IREF1RC_OFFSET_MASK, 0xe4 << IREF1RC_OFFSET_SHIFT,
537-
"BXT_PORT_CL1CM_DW10(%d)", phy);
536+
IREF1RC_OFFSET_MASK, IREF1RC_OFFSET(0xe4),
537+
"BXT_PORT_CL1CM_DW10(%d)", phy);
538538

539539
/* Power gating */
540540
mask = OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN | SUS_CLK_CONFIG;
541541
ok &= _CHK(BXT_PORT_CL1CM_DW28(phy), mask, mask,
542-
"BXT_PORT_CL1CM_DW28(%d)", phy);
542+
"BXT_PORT_CL1CM_DW28(%d)", phy);
543543

544544
if (phy_info->dual_channel)
545545
ok &= _CHK(BXT_PORT_CL2CM_DW6(phy),
@@ -549,17 +549,17 @@ bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
549549
if (phy_info->rcomp_phy != -1) {
550550
u32 grc_code = dev_priv->display.state.bxt_phy_grc;
551551

552-
grc_code = grc_code << GRC_CODE_FAST_SHIFT |
553-
grc_code << GRC_CODE_SLOW_SHIFT |
554-
grc_code;
552+
grc_code = GRC_CODE_FAST(grc_code) |
553+
GRC_CODE_SLOW(grc_code) |
554+
GRC_CODE_NOM(grc_code);
555555
mask = GRC_CODE_FAST_MASK | GRC_CODE_SLOW_MASK |
556556
GRC_CODE_NOM_MASK;
557557
ok &= _CHK(BXT_PORT_REF_DW6(phy), mask, grc_code,
558558
"BXT_PORT_REF_DW6(%d)", phy);
559559

560560
mask = GRC_DIS | GRC_RDY_OVRD;
561561
ok &= _CHK(BXT_PORT_REF_DW8(phy), mask, mask,
562-
"BXT_PORT_REF_DW8(%d)", phy);
562+
"BXT_PORT_REF_DW8(%d)", phy);
563563
}
564564

565565
return ok;

‎drivers/gpu/drm/i915/i915_reg.h

Lines changed: 37 additions & 37 deletions
Original file line numberDiff line numberDiff line change
@@ -648,32 +648,32 @@
648648
/* BXT PHY common lane registers */
649649
#define _PORT_CL1CM_DW0_A 0x162000
650650
#define _PORT_CL1CM_DW0_BC 0x6C000
651-
#define PHY_POWER_GOOD (1 << 16)
652-
#define PHY_RESERVED (1 << 7)
651+
#define PHY_POWER_GOOD REG_BIT(16)
652+
#define PHY_RESERVED REG_BIT(7)
653653
#define BXT_PORT_CL1CM_DW0(phy) _BXT_PHY((phy), _PORT_CL1CM_DW0_BC)
654654

655655
#define _PORT_CL1CM_DW9_A 0x162024
656656
#define _PORT_CL1CM_DW9_BC 0x6C024
657-
#define IREF0RC_OFFSET_SHIFT 8
658-
#define IREF0RC_OFFSET_MASK (0xFF << IREF0RC_OFFSET_SHIFT)
657+
#define IREF0RC_OFFSET_MASK REG_GENMASK(15, 8)
658+
#define IREF0RC_OFFSET(x) REG_FIELD_PREP(IREF0RC_OFFSET_MASK, (x))
659659
#define BXT_PORT_CL1CM_DW9(phy) _BXT_PHY((phy), _PORT_CL1CM_DW9_BC)
660660

661661
#define _PORT_CL1CM_DW10_A 0x162028
662662
#define _PORT_CL1CM_DW10_BC 0x6C028
663-
#define IREF1RC_OFFSET_SHIFT 8
664-
#define IREF1RC_OFFSET_MASK (0xFF << IREF1RC_OFFSET_SHIFT)
663+
#define IREF1RC_OFFSET_MASK REG_GENMASK(15, 8)
664+
#define IREF1RC_OFFSET(x) REG_FIELD_PREP(IREF1RC_OFFSET_MASK, (x))
665665
#define BXT_PORT_CL1CM_DW10(phy) _BXT_PHY((phy), _PORT_CL1CM_DW10_BC)
666666

667667
#define _PORT_CL1CM_DW28_A 0x162070
668668
#define _PORT_CL1CM_DW28_BC 0x6C070
669-
#define OCL1_POWER_DOWN_EN (1 << 23)
670-
#define DW28_OLDO_DYN_PWR_DOWN_EN (1 << 22)
671-
#define SUS_CLK_CONFIG 0x3
669+
#define OCL1_POWER_DOWN_EN REG_BIT(23)
670+
#define DW28_OLDO_DYN_PWR_DOWN_EN REG_BIT(22)
671+
#define SUS_CLK_CONFIG REG_GENMASK(1, 0)
672672
#define BXT_PORT_CL1CM_DW28(phy) _BXT_PHY((phy), _PORT_CL1CM_DW28_BC)
673673

674674
#define _PORT_CL1CM_DW30_A 0x162078
675675
#define _PORT_CL1CM_DW30_BC 0x6C078
676-
#define OCL2_LDOFUSE_PWR_DIS (1 << 6)
676+
#define OCL2_LDOFUSE_PWR_DIS REG_BIT(6)
677677
#define BXT_PORT_CL1CM_DW30(phy) _BXT_PHY((phy), _PORT_CL1CM_DW30_BC)
678678

679679
/* The spec defines this only for BXT PHY0, but lets assume that this
@@ -682,29 +682,30 @@
682682
#define _PORT_CL2CM_DW6_A 0x162358
683683
#define _PORT_CL2CM_DW6_BC 0x6C358
684684
#define BXT_PORT_CL2CM_DW6(phy) _BXT_PHY((phy), _PORT_CL2CM_DW6_BC)
685-
#define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28)
685+
#define DW6_OLDO_DYN_PWR_DOWN_EN REG_BIT(28)
686686

687687
/* BXT PHY Ref registers */
688688
#define _PORT_REF_DW3_A 0x16218C
689689
#define _PORT_REF_DW3_BC 0x6C18C
690-
#define GRC_DONE (1 << 22)
690+
#define GRC_DONE REG_BIT(22)
691691
#define BXT_PORT_REF_DW3(phy) _BXT_PHY((phy), _PORT_REF_DW3_BC)
692692

693693
#define _PORT_REF_DW6_A 0x162198
694694
#define _PORT_REF_DW6_BC 0x6C198
695-
#define GRC_CODE_SHIFT 24
696-
#define GRC_CODE_MASK (0xFF << GRC_CODE_SHIFT)
697-
#define GRC_CODE_FAST_SHIFT 16
698-
#define GRC_CODE_FAST_MASK (0xFF << GRC_CODE_FAST_SHIFT)
699-
#define GRC_CODE_SLOW_SHIFT 8
700-
#define GRC_CODE_SLOW_MASK (0xFF << GRC_CODE_SLOW_SHIFT)
701-
#define GRC_CODE_NOM_MASK 0xFF
695+
#define GRC_CODE_MASK REG_GENMASK(31, 24)
696+
#define GRC_CODE(x) REG_FIELD_PREP(GRC_CODE_MASK, (x))
697+
#define GRC_CODE_FAST_MASK REG_GENMASK(23, 16)
698+
#define GRC_CODE_FAST(x) REG_FIELD_PREP(GRC_CODE_FAST_MASK, (x))
699+
#define GRC_CODE_SLOW_MASK REG_GENMASK(15, 8)
700+
#define GRC_CODE_SLOW(x) REG_FIELD_PREP(GRC_CODE_SLOW_MASK, (x))
701+
#define GRC_CODE_NOM_MASK REG_GENMASK(7, 0)
702+
#define GRC_CODE_NOM(x) REG_FIELD_PREP(GRC_CODE_NOM_MASK, (x))
702703
#define BXT_PORT_REF_DW6(phy) _BXT_PHY((phy), _PORT_REF_DW6_BC)
703704

704705
#define _PORT_REF_DW8_A 0x1621A0
705706
#define _PORT_REF_DW8_BC 0x6C1A0
706-
#define GRC_DIS (1 << 15)
707-
#define GRC_RDY_OVRD (1 << 1)
707+
#define GRC_DIS REG_BIT(15)
708+
#define GRC_RDY_OVRD REG_BIT(1)
708709
#define BXT_PORT_REF_DW8(phy) _BXT_PHY((phy), _PORT_REF_DW8_BC)
709710

710711
/* BXT PHY PCS registers */
@@ -721,8 +722,8 @@
721722
_PORT_PCS_DW10_GRP_B, \
722723
_PORT_PCS_DW10_GRP_C)
723724

724-
#define TX2_SWING_CALC_INIT (1 << 31)
725-
#define TX1_SWING_CALC_INIT (1 << 30)
725+
#define TX2_SWING_CALC_INIT REG_BIT(31)
726+
#define TX1_SWING_CALC_INIT REG_BIT(30)
726727

727728
#define _PORT_PCS_DW12_LN01_A 0x162430
728729
#define _PORT_PCS_DW12_LN01_B 0x6C430
@@ -733,8 +734,8 @@
733734
#define _PORT_PCS_DW12_GRP_A 0x162c30
734735
#define _PORT_PCS_DW12_GRP_B 0x6CC30
735736
#define _PORT_PCS_DW12_GRP_C 0x6CE30
736-
#define LANESTAGGER_STRAP_OVRD (1 << 6)
737-
#define LANE_STAGGER_MASK 0x1F
737+
#define LANESTAGGER_STRAP_OVRD REG_BIT(6)
738+
#define LANE_STAGGER_MASK REG_GENMASK(4, 0)
738739
#define BXT_PORT_PCS_DW12_LN01(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
739740
_PORT_PCS_DW12_LN01_B, \
740741
_PORT_PCS_DW12_LN01_C)
@@ -761,10 +762,10 @@
761762
#define BXT_PORT_TX_DW2_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
762763
_PORT_TX_DW2_GRP_B, \
763764
_PORT_TX_DW2_GRP_C)
764-
#define MARGIN_000_SHIFT 16
765-
#define MARGIN_000 (0xFF << MARGIN_000_SHIFT)
766-
#define UNIQ_TRANS_SCALE_SHIFT 8
767-
#define UNIQ_TRANS_SCALE (0xFF << UNIQ_TRANS_SCALE_SHIFT)
765+
#define MARGIN_000_MASK REG_GENMASK(23, 16)
766+
#define MARGIN_000(x) REG_FIELD_PREP(MARGIN_000_MASK, (x))
767+
#define UNIQ_TRANS_SCALE_MASK REG_GENMASK(15, 8)
768+
#define UNIQ_TRANS_SCALE(x) REG_FIELD_PREP(UNIQ_TRANS_SCALE_MASK, (x))
768769

769770
#define _PORT_TX_DW3_LN0_A 0x16250C
770771
#define _PORT_TX_DW3_LN0_B 0x6C50C
@@ -778,8 +779,8 @@
778779
#define BXT_PORT_TX_DW3_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
779780
_PORT_TX_DW3_GRP_B, \
780781
_PORT_TX_DW3_GRP_C)
781-
#define SCALE_DCOMP_METHOD (1 << 26)
782-
#define UNIQUE_TRANGE_EN_METHOD (1 << 27)
782+
#define SCALE_DCOMP_METHOD REG_BIT(26)
783+
#define UNIQUE_TRANGE_EN_METHOD REG_BIT(27)
783784

784785
#define _PORT_TX_DW4_LN0_A 0x162510
785786
#define _PORT_TX_DW4_LN0_B 0x6C510
@@ -793,8 +794,8 @@
793794
#define BXT_PORT_TX_DW4_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
794795
_PORT_TX_DW4_GRP_B, \
795796
_PORT_TX_DW4_GRP_C)
796-
#define DEEMPH_SHIFT 24
797-
#define DE_EMPHASIS (0xFF << DEEMPH_SHIFT)
797+
#define DE_EMPHASIS_MASK REG_GENMASK(31, 24)
798+
#define DE_EMPHASIS(x) REG_FIELD_PREP(DE_EMPHASIS_MASK, (x))
798799

799800
#define _PORT_TX_DW5_LN0_A 0x162514
800801
#define _PORT_TX_DW5_LN0_B 0x6C514
@@ -808,14 +809,13 @@
808809
#define BXT_PORT_TX_DW5_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
809810
_PORT_TX_DW5_GRP_B, \
810811
_PORT_TX_DW5_GRP_C)
811-
#define DCC_DELAY_RANGE_1 (1 << 9)
812-
#define DCC_DELAY_RANGE_2 (1 << 8)
812+
#define DCC_DELAY_RANGE_1 REG_BIT(9)
813+
#define DCC_DELAY_RANGE_2 REG_BIT(8)
813814

814815
#define _PORT_TX_DW14_LN0_A 0x162538
815816
#define _PORT_TX_DW14_LN0_B 0x6C538
816817
#define _PORT_TX_DW14_LN0_C 0x6C938
817-
#define LATENCY_OPTIM_SHIFT 30
818-
#define LATENCY_OPTIM (1 << LATENCY_OPTIM_SHIFT)
818+
#define LATENCY_OPTIM REG_BIT(30)
819819
#define BXT_PORT_TX_DW14_LN(phy, ch, lane) \
820820
_MMIO(_BXT_PHY_CH(phy, ch, _PORT_TX_DW14_LN0_B, \
821821
_PORT_TX_DW14_LN0_C) + \

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