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yamahatasean-jc
yamahata
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sean-jc
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KVM: selftests: Add test for configure of x86 APIC bus frequency
Test if KVM emulates the APIC bus clock at the expected frequency when userspace configures the frequency via KVM_CAP_X86_APIC_BUS_CYCLES_NS. Set APIC timer's initial count to the maximum value and busy wait for 100 msec (largely arbitrary) using the TSC. Read the APIC timer's "current count" to calculate the actual APIC bus clock frequency based on TSC frequency. Suggested-by: Sean Christopherson <[email protected]> Signed-off-by: Isaku Yamahata <[email protected]> Co-developed-by: Reinette Chatre <[email protected]> Signed-off-by: Reinette Chatre <[email protected]> Link: https://lore.kernel.org/r/2fccf35715b5ba8aec5e5708d86ad7015b8d74e6.1718214999.git.reinette.chatre@intel.com Signed-off-by: Sean Christopherson <[email protected]>
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‎tools/testing/selftests/kvm/Makefile

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@@ -112,6 +112,7 @@ TEST_GEN_PROGS_x86_64 += x86_64/vmx_invalid_nested_guest_state
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TEST_GEN_PROGS_x86_64 += x86_64/vmx_set_nested_state_test
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TEST_GEN_PROGS_x86_64 += x86_64/vmx_tsc_adjust_test
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TEST_GEN_PROGS_x86_64 += x86_64/vmx_nested_tsc_scaling_test
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TEST_GEN_PROGS_x86_64 += x86_64/apic_bus_clock_test
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TEST_GEN_PROGS_x86_64 += x86_64/xapic_ipi_test
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TEST_GEN_PROGS_x86_64 += x86_64/xapic_state_test
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TEST_GEN_PROGS_x86_64 += x86_64/xcr0_cpuid_test

‎tools/testing/selftests/kvm/include/x86_64/apic.h

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#define APIC_VECTOR_MASK 0x000FF
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#define APIC_ICR2 0x310
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#define SET_APIC_DEST_FIELD(x) ((x) << 24)
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#define APIC_LVTT 0x320
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#define APIC_LVT_TIMER_ONESHOT (0 << 17)
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#define APIC_LVT_TIMER_PERIODIC (1 << 17)
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#define APIC_LVT_TIMER_TSCDEADLINE (2 << 17)
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#define APIC_LVT_MASKED (1 << 16)
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#define APIC_TMICT 0x380
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#define APIC_TMCCT 0x390
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#define APIC_TDCR 0x3E0
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void apic_disable(void);
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void xapic_enable(void);

‎tools/testing/selftests/kvm/x86_64/apic_bus_clock_test.c

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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2024 Intel Corporation
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*
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* Verify KVM correctly emulates the APIC bus frequency when the VMM configures
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* the frequency via KVM_CAP_X86_APIC_BUS_CYCLES_NS. Start the APIC timer by
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* programming TMICT (timer initial count) to the largest value possible (so
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* that the timer will not expire during the test). Then, after an arbitrary
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* amount of time has elapsed, verify TMCCT (timer current count) is within 1%
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* of the expected value based on the time elapsed, the APIC bus frequency, and
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* the programmed TDCR (timer divide configuration register).
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*/
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#include "apic.h"
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#include "test_util.h"
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/*
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* Possible TDCR values with matching divide count. Used to modify APIC
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* timer frequency.
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*/
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static const struct {
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const uint32_t tdcr;
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const uint32_t divide_count;
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} tdcrs[] = {
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{0x0, 2},
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{0x1, 4},
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{0x2, 8},
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{0x3, 16},
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{0x8, 32},
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{0x9, 64},
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{0xa, 128},
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{0xb, 1},
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};
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static bool is_x2apic;
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static void apic_enable(void)
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{
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if (is_x2apic)
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x2apic_enable();
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else
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xapic_enable();
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}
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static uint32_t apic_read_reg(unsigned int reg)
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{
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return is_x2apic ? x2apic_read_reg(reg) : xapic_read_reg(reg);
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}
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static void apic_write_reg(unsigned int reg, uint32_t val)
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{
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if (is_x2apic)
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x2apic_write_reg(reg, val);
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else
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xapic_write_reg(reg, val);
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}
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static void apic_guest_code(uint64_t apic_hz, uint64_t delay_ms)
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{
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uint64_t tsc_hz = guest_tsc_khz * 1000;
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const uint32_t tmict = ~0u;
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uint64_t tsc0, tsc1, freq;
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uint32_t tmcct;
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int i;
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apic_enable();
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/*
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* Setup one-shot timer. The vector does not matter because the
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* interrupt should not fire.
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*/
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apic_write_reg(APIC_LVTT, APIC_LVT_TIMER_ONESHOT | APIC_LVT_MASKED);
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for (i = 0; i < ARRAY_SIZE(tdcrs); i++) {
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apic_write_reg(APIC_TDCR, tdcrs[i].tdcr);
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apic_write_reg(APIC_TMICT, tmict);
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tsc0 = rdtsc();
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udelay(delay_ms * 1000);
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tmcct = apic_read_reg(APIC_TMCCT);
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tsc1 = rdtsc();
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/*
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* Stop the timer _after_ reading the current, final count, as
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* writing the initial counter also modifies the current count.
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*/
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apic_write_reg(APIC_TMICT, 0);
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freq = (tmict - tmcct) * tdcrs[i].divide_count * tsc_hz / (tsc1 - tsc0);
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/* Check if measured frequency is within 5% of configured frequency. */
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__GUEST_ASSERT(freq < apic_hz * 105 / 100 && freq > apic_hz * 95 / 100,
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"Frequency = %lu (wanted %lu - %lu), bus = %lu, div = %u, tsc = %lu",
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freq, apic_hz * 95 / 100, apic_hz * 105 / 100,
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apic_hz, tdcrs[i].divide_count, tsc_hz);
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}
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GUEST_DONE();
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}
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static void test_apic_bus_clock(struct kvm_vcpu *vcpu)
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{
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bool done = false;
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struct ucall uc;
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while (!done) {
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vcpu_run(vcpu);
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TEST_ASSERT_KVM_EXIT_REASON(vcpu, KVM_EXIT_IO);
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switch (get_ucall(vcpu, &uc)) {
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case UCALL_DONE:
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done = true;
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break;
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case UCALL_ABORT:
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REPORT_GUEST_ASSERT(uc);
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break;
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default:
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TEST_FAIL("Unknown ucall %lu", uc.cmd);
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break;
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}
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}
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}
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static void run_apic_bus_clock_test(uint64_t apic_hz, uint64_t delay_ms,
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bool x2apic)
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{
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struct kvm_vcpu *vcpu;
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struct kvm_vm *vm;
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int ret;
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is_x2apic = x2apic;
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vm = vm_create(1);
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sync_global_to_guest(vm, is_x2apic);
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vm_enable_cap(vm, KVM_CAP_X86_APIC_BUS_CYCLES_NS,
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NSEC_PER_SEC / apic_hz);
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vcpu = vm_vcpu_add(vm, 0, apic_guest_code);
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vcpu_args_set(vcpu, 2, apic_hz, delay_ms);
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ret = __vm_enable_cap(vm, KVM_CAP_X86_APIC_BUS_CYCLES_NS,
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NSEC_PER_SEC / apic_hz);
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TEST_ASSERT(ret < 0 && errno == EINVAL,
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"Setting of APIC bus frequency after vCPU is created should fail.");
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if (!is_x2apic)
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virt_pg_map(vm, APIC_DEFAULT_GPA, APIC_DEFAULT_GPA);
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test_apic_bus_clock(vcpu);
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kvm_vm_free(vm);
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}
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static void help(char *name)
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{
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puts("");
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printf("usage: %s [-h] [-d delay] [-f APIC bus freq]\n", name);
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puts("");
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printf("-d: Delay (in msec) guest uses to measure APIC bus frequency.\n");
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printf("-f: The APIC bus frequency (in MHz) to be configured for the guest.\n");
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puts("");
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}
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int main(int argc, char *argv[])
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{
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/*
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* Arbitrarilty default to 25MHz for the APIC bus frequency, which is
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* different enough from the default 1GHz to be interesting.
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*/
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uint64_t apic_hz = 25 * 1000 * 1000;
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uint64_t delay_ms = 100;
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int opt;
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TEST_REQUIRE(kvm_has_cap(KVM_CAP_X86_APIC_BUS_CYCLES_NS));
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while ((opt = getopt(argc, argv, "d:f:h")) != -1) {
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switch (opt) {
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case 'f':
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apic_hz = atoi_positive("APIC bus frequency", optarg) * 1000 * 1000;
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break;
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case 'd':
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delay_ms = atoi_positive("Delay in milliseconds", optarg);
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break;
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case 'h':
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default:
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help(argv[0]);
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exit(KSFT_SKIP);
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}
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}
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run_apic_bus_clock_test(apic_hz, delay_ms, false);
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run_apic_bus_clock_test(apic_hz, delay_ms, true);
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}

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