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40 | 40 | #define L23_CLK_RMV_DIS BIT(2)
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41 | 41 | #define L1_CLK_RMV_DIS BIT(1)
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42 | 42 |
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43 |
| -#define PCIE20_COMMAND_STATUS 0x04 |
44 |
| -#define CMD_BME_VAL 0x4 |
45 |
| -#define PCIE20_DEVICE_CONTROL2_STATUS2 0x98 |
46 |
| -#define PCIE_CAP_CPL_TIMEOUT_DISABLE 0x10 |
47 |
| - |
48 | 43 | #define PCIE20_PARF_PHY_CTRL 0x40
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49 | 44 | #define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK GENMASK(20, 16)
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50 | 45 | #define PHY_CTRL_PHY_TX0_TERM_OFFSET(x) ((x) << 16)
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73 | 68 | #define CFG_BRIDGE_SB_INIT BIT(0)
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74 | 69 |
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75 | 70 | #define PCIE20_CAP 0x70
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76 |
| -#define PCIE20_CAP_LINK_CAPABILITIES (PCIE20_CAP + 0xC) |
77 |
| -#define PCIE20_CAP_ACTIVE_STATE_LINK_PM_SUPPORT (BIT(10) | BIT(11)) |
| 71 | +#define PCIE20_DEVICE_CONTROL2_STATUS2 (PCIE20_CAP + PCI_EXP_DEVCTL2) |
| 72 | +#define PCIE20_CAP_LINK_CAPABILITIES (PCIE20_CAP + PCI_EXP_LNKCAP) |
78 | 73 | #define PCIE20_CAP_LINK_1 (PCIE20_CAP + 0x14)
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79 | 74 | #define PCIE_CAP_LINK1_VAL 0x2FD7F
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80 | 75 |
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@@ -1095,15 +1090,15 @@ static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie)
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1095 | 1090 | pcie->parf + PCIE20_PARF_SYS_CTRL);
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1096 | 1091 | writel(0, pcie->parf + PCIE20_PARF_Q2A_FLUSH);
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1097 | 1092 |
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1098 |
| - writel(CMD_BME_VAL, pci->dbi_base + PCIE20_COMMAND_STATUS); |
| 1093 | + writel(PCI_COMMAND_MASTER, pci->dbi_base + PCI_COMMAND); |
1099 | 1094 | writel(DBI_RO_WR_EN, pci->dbi_base + PCIE20_MISC_CONTROL_1_REG);
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1100 | 1095 | writel(PCIE_CAP_LINK1_VAL, pci->dbi_base + PCIE20_CAP_LINK_1);
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1101 | 1096 |
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1102 | 1097 | val = readl(pci->dbi_base + PCIE20_CAP_LINK_CAPABILITIES);
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1103 |
| - val &= ~PCIE20_CAP_ACTIVE_STATE_LINK_PM_SUPPORT; |
| 1098 | + val &= ~PCI_EXP_LNKCAP_ASPMS; |
1104 | 1099 | writel(val, pci->dbi_base + PCIE20_CAP_LINK_CAPABILITIES);
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1105 | 1100 |
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1106 |
| - writel(PCIE_CAP_CPL_TIMEOUT_DISABLE, pci->dbi_base + |
| 1101 | + writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + |
1107 | 1102 | PCIE20_DEVICE_CONTROL2_STATUS2);
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1108 | 1103 |
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1109 | 1104 | return 0;
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