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Commit 824001c

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AnsuelLorenzo Pieralisi
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PCI: qcom: Replace define with standard value
Lots of define are actually already defined in pci_regs.h, directly use the standard defines. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Ansuel Smith <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Stanimir Varbanov <[email protected]>
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drivers/pci/controller/dwc/pcie-qcom.c

Lines changed: 5 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -40,11 +40,6 @@
4040
#define L23_CLK_RMV_DIS BIT(2)
4141
#define L1_CLK_RMV_DIS BIT(1)
4242

43-
#define PCIE20_COMMAND_STATUS 0x04
44-
#define CMD_BME_VAL 0x4
45-
#define PCIE20_DEVICE_CONTROL2_STATUS2 0x98
46-
#define PCIE_CAP_CPL_TIMEOUT_DISABLE 0x10
47-
4843
#define PCIE20_PARF_PHY_CTRL 0x40
4944
#define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK GENMASK(20, 16)
5045
#define PHY_CTRL_PHY_TX0_TERM_OFFSET(x) ((x) << 16)
@@ -73,8 +68,8 @@
7368
#define CFG_BRIDGE_SB_INIT BIT(0)
7469

7570
#define PCIE20_CAP 0x70
76-
#define PCIE20_CAP_LINK_CAPABILITIES (PCIE20_CAP + 0xC)
77-
#define PCIE20_CAP_ACTIVE_STATE_LINK_PM_SUPPORT (BIT(10) | BIT(11))
71+
#define PCIE20_DEVICE_CONTROL2_STATUS2 (PCIE20_CAP + PCI_EXP_DEVCTL2)
72+
#define PCIE20_CAP_LINK_CAPABILITIES (PCIE20_CAP + PCI_EXP_LNKCAP)
7873
#define PCIE20_CAP_LINK_1 (PCIE20_CAP + 0x14)
7974
#define PCIE_CAP_LINK1_VAL 0x2FD7F
8075

@@ -1095,15 +1090,15 @@ static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie)
10951090
pcie->parf + PCIE20_PARF_SYS_CTRL);
10961091
writel(0, pcie->parf + PCIE20_PARF_Q2A_FLUSH);
10971092

1098-
writel(CMD_BME_VAL, pci->dbi_base + PCIE20_COMMAND_STATUS);
1093+
writel(PCI_COMMAND_MASTER, pci->dbi_base + PCI_COMMAND);
10991094
writel(DBI_RO_WR_EN, pci->dbi_base + PCIE20_MISC_CONTROL_1_REG);
11001095
writel(PCIE_CAP_LINK1_VAL, pci->dbi_base + PCIE20_CAP_LINK_1);
11011096

11021097
val = readl(pci->dbi_base + PCIE20_CAP_LINK_CAPABILITIES);
1103-
val &= ~PCIE20_CAP_ACTIVE_STATE_LINK_PM_SUPPORT;
1098+
val &= ~PCI_EXP_LNKCAP_ASPMS;
11041099
writel(val, pci->dbi_base + PCIE20_CAP_LINK_CAPABILITIES);
11051100

1106-
writel(PCIE_CAP_CPL_TIMEOUT_DISABLE, pci->dbi_base +
1101+
writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base +
11071102
PCIE20_DEVICE_CONTROL2_STATUS2);
11081103

11091104
return 0;

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