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Merge tag 'drm-fixes-2022-01-28' of git://anongit.freedesktop.org/drm/drm
Pull drm fixes from Dave Airlie: "This week's regular normal fixes. amdgpu and msm make up the bulk of it, with a scattering of fixes elsewhere. atomic: - fix CRTC handling during modeset privcy-screen: - honor acpi=off ttm: - build fix for um panel: - add orientation quirk for 1NetBook OneXPlayer amdgpu: - Proper fix for otg synchronization logic regression - DCN3.01 fixes - Filter out secondary radeon PCI IDs - udelay fixes - Fix a memory leak in an error path msm: - parameter check fixes - put_device balancing - idle/suspend fixes etnaviv: - relax submit size checks vc4: - fix potential deadlock in DSI code ast: - revert 1600x900 mode change" * tag 'drm-fixes-2022-01-28' of git://anongit.freedesktop.org/drm/drm: (25 commits) drm/privacy-screen: honor acpi=off in detect_thinkpad_privacy_screen Revert "drm/ast: Support 1600x900 with 108MHz PCLK" drm/amdgpu/display: Remove t_srx_delay_us. drm/amd/display: Wrap dcn301_calculate_wm_and_dlg for FPU. drm/amd/display: Fix FP start/end for dcn30_internal_validate_bw. drm/amd/display/dc/calcs/dce_calcs: Fix a memleak in calculate_bandwidth() drm/amdgpu/display: use msleep rather than udelay for long delays drm/amdgpu/display: adjust msleep limit in dp_wait_for_training_aux_rd_interval drm/amdgpu: filter out radeon secondary ids as well drm/amd/display: change FIFO reset condition to embedded display only drm/amd/display: Correct MPC split policy for DCN301 drm/amd/display: Fix for otg synchronization logic drm/etnaviv: relax submit size limits drm/msm/gpu: Cancel idle/boost work on suspend drm/msm/gpu: Wait for idle before suspending drm/atomic: Add the crtc to affected crtc only if uapi.enable = true drm/msm/dsi: invalid parameter check in msm_dsi_phy_enable drm/msm/a6xx: Add missing suspend_count increment drm/msm: Fix wrong size calculation drm/msm/dpu: invalid parameter check in dpu_setup_dspp_pcc ...
2 parents 23a4642 + db5aa14 commit 82b550f

38 files changed

+307
-70
lines changed

‎drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

Lines changed: 81 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1525,6 +1525,87 @@ static const u16 amdgpu_unsupported_pciidlist[] = {
15251525
0x99A0,
15261526
0x99A2,
15271527
0x99A4,
1528+
/* radeon secondary ids */
1529+
0x3171,
1530+
0x3e70,
1531+
0x4164,
1532+
0x4165,
1533+
0x4166,
1534+
0x4168,
1535+
0x4170,
1536+
0x4171,
1537+
0x4172,
1538+
0x4173,
1539+
0x496e,
1540+
0x4a69,
1541+
0x4a6a,
1542+
0x4a6b,
1543+
0x4a70,
1544+
0x4a74,
1545+
0x4b69,
1546+
0x4b6b,
1547+
0x4b6c,
1548+
0x4c6e,
1549+
0x4e64,
1550+
0x4e65,
1551+
0x4e66,
1552+
0x4e67,
1553+
0x4e68,
1554+
0x4e69,
1555+
0x4e6a,
1556+
0x4e71,
1557+
0x4f73,
1558+
0x5569,
1559+
0x556b,
1560+
0x556d,
1561+
0x556f,
1562+
0x5571,
1563+
0x5854,
1564+
0x5874,
1565+
0x5940,
1566+
0x5941,
1567+
0x5b72,
1568+
0x5b73,
1569+
0x5b74,
1570+
0x5b75,
1571+
0x5d44,
1572+
0x5d45,
1573+
0x5d6d,
1574+
0x5d6f,
1575+
0x5d72,
1576+
0x5d77,
1577+
0x5e6b,
1578+
0x5e6d,
1579+
0x7120,
1580+
0x7124,
1581+
0x7129,
1582+
0x712e,
1583+
0x712f,
1584+
0x7162,
1585+
0x7163,
1586+
0x7166,
1587+
0x7167,
1588+
0x7172,
1589+
0x7173,
1590+
0x71a0,
1591+
0x71a1,
1592+
0x71a3,
1593+
0x71a7,
1594+
0x71bb,
1595+
0x71e0,
1596+
0x71e1,
1597+
0x71e2,
1598+
0x71e6,
1599+
0x71e7,
1600+
0x71f2,
1601+
0x7269,
1602+
0x726b,
1603+
0x726e,
1604+
0x72a0,
1605+
0x72a8,
1606+
0x72b1,
1607+
0x72b3,
1608+
0x793f,
15281609
};
15291610

15301611
static const struct pci_device_id pciidlist[] = {

‎drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2033,10 +2033,10 @@ static void calculate_bandwidth(
20332033
kfree(surface_type);
20342034
free_tiling_mode:
20352035
kfree(tiling_mode);
2036-
free_yclk:
2037-
kfree(yclk);
20382036
free_sclk:
20392037
kfree(sclk);
2038+
free_yclk:
2039+
kfree(yclk);
20402040
}
20412041

20422042
/*******************************************************************************

‎drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -503,7 +503,6 @@ static void dcn_bw_calc_rq_dlg_ttu(
503503
//input[in_idx].dout.output_standard;
504504

505505
/*todo: soc->sr_enter_plus_exit_time??*/
506-
dlg_sys_param->t_srx_delay_us = dc->dcn_ip->dcfclk_cstate_latency / v->dcf_clk_deep_sleep;
507506

508507
dml1_rq_dlg_get_rq_params(dml, rq_param, &input->pipe.src);
509508
dml1_extract_rq_regs(dml, rq_regs, rq_param);

‎drivers/gpu/drm/amd/display/dc/core/dc.c

Lines changed: 27 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -1404,20 +1404,34 @@ static void program_timing_sync(
14041404
status->timing_sync_info.master = false;
14051405

14061406
}
1407-
/* remove any other unblanked pipes as they have already been synced */
1408-
for (j = j + 1; j < group_size; j++) {
1409-
bool is_blanked;
14101407

1411-
if (pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked)
1412-
is_blanked =
1413-
pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked(pipe_set[j]->stream_res.opp);
1414-
else
1415-
is_blanked =
1416-
pipe_set[j]->stream_res.tg->funcs->is_blanked(pipe_set[j]->stream_res.tg);
1417-
if (!is_blanked) {
1418-
group_size--;
1419-
pipe_set[j] = pipe_set[group_size];
1420-
j--;
1408+
/* remove any other pipes that are already been synced */
1409+
if (dc->config.use_pipe_ctx_sync_logic) {
1410+
/* check pipe's syncd to decide which pipe to be removed */
1411+
for (j = 1; j < group_size; j++) {
1412+
if (pipe_set[j]->pipe_idx_syncd == pipe_set[0]->pipe_idx_syncd) {
1413+
group_size--;
1414+
pipe_set[j] = pipe_set[group_size];
1415+
j--;
1416+
} else
1417+
/* link slave pipe's syncd with master pipe */
1418+
pipe_set[j]->pipe_idx_syncd = pipe_set[0]->pipe_idx_syncd;
1419+
}
1420+
} else {
1421+
for (j = j + 1; j < group_size; j++) {
1422+
bool is_blanked;
1423+
1424+
if (pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked)
1425+
is_blanked =
1426+
pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked(pipe_set[j]->stream_res.opp);
1427+
else
1428+
is_blanked =
1429+
pipe_set[j]->stream_res.tg->funcs->is_blanked(pipe_set[j]->stream_res.tg);
1430+
if (!is_blanked) {
1431+
group_size--;
1432+
pipe_set[j] = pipe_set[group_size];
1433+
j--;
1434+
}
14211435
}
14221436
}
14231437

‎drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -202,7 +202,7 @@ void dp_wait_for_training_aux_rd_interval(
202202
uint32_t wait_in_micro_secs)
203203
{
204204
#if defined(CONFIG_DRM_AMD_DC_DCN)
205-
if (wait_in_micro_secs > 16000)
205+
if (wait_in_micro_secs > 1000)
206206
msleep(wait_in_micro_secs/1000);
207207
else
208208
udelay(wait_in_micro_secs);
@@ -6935,7 +6935,7 @@ bool dpcd_write_128b_132b_sst_payload_allocation_table(
69356935
}
69366936
}
69376937
retries++;
6938-
udelay(5000);
6938+
msleep(5);
69396939
}
69406940

69416941
if (!result && retries == max_retries) {
@@ -6987,7 +6987,7 @@ bool dpcd_poll_for_allocation_change_trigger(struct dc_link *link)
69876987
break;
69886988
}
69896989

6990-
udelay(5000);
6990+
msleep(5);
69916991
}
69926992

69936993
if (result == ACT_FAILED) {

‎drivers/gpu/drm/amd/display/dc/core/dc_resource.c

Lines changed: 54 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3217,6 +3217,60 @@ struct hpo_dp_link_encoder *resource_get_hpo_dp_link_enc_for_det_lt(
32173217
}
32183218
#endif
32193219

3220+
void reset_syncd_pipes_from_disabled_pipes(struct dc *dc,
3221+
struct dc_state *context)
3222+
{
3223+
int i, j;
3224+
struct pipe_ctx *pipe_ctx_old, *pipe_ctx, *pipe_ctx_syncd;
3225+
3226+
/* If pipe backend is reset, need to reset pipe syncd status */
3227+
for (i = 0; i < dc->res_pool->pipe_count; i++) {
3228+
pipe_ctx_old = &dc->current_state->res_ctx.pipe_ctx[i];
3229+
pipe_ctx = &context->res_ctx.pipe_ctx[i];
3230+
3231+
if (!pipe_ctx_old->stream)
3232+
continue;
3233+
3234+
if (pipe_ctx_old->top_pipe || pipe_ctx_old->prev_odm_pipe)
3235+
continue;
3236+
3237+
if (!pipe_ctx->stream ||
3238+
pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
3239+
3240+
/* Reset all the syncd pipes from the disabled pipe */
3241+
for (j = 0; j < dc->res_pool->pipe_count; j++) {
3242+
pipe_ctx_syncd = &context->res_ctx.pipe_ctx[j];
3243+
if ((GET_PIPE_SYNCD_FROM_PIPE(pipe_ctx_syncd) == pipe_ctx_old->pipe_idx) ||
3244+
!IS_PIPE_SYNCD_VALID(pipe_ctx_syncd))
3245+
SET_PIPE_SYNCD_TO_PIPE(pipe_ctx_syncd, j);
3246+
}
3247+
}
3248+
}
3249+
}
3250+
3251+
void check_syncd_pipes_for_disabled_master_pipe(struct dc *dc,
3252+
struct dc_state *context,
3253+
uint8_t disabled_master_pipe_idx)
3254+
{
3255+
int i;
3256+
struct pipe_ctx *pipe_ctx, *pipe_ctx_check;
3257+
3258+
pipe_ctx = &context->res_ctx.pipe_ctx[disabled_master_pipe_idx];
3259+
if ((GET_PIPE_SYNCD_FROM_PIPE(pipe_ctx) != disabled_master_pipe_idx) ||
3260+
!IS_PIPE_SYNCD_VALID(pipe_ctx))
3261+
SET_PIPE_SYNCD_TO_PIPE(pipe_ctx, disabled_master_pipe_idx);
3262+
3263+
/* for the pipe disabled, check if any slave pipe exists and assert */
3264+
for (i = 0; i < dc->res_pool->pipe_count; i++) {
3265+
pipe_ctx_check = &context->res_ctx.pipe_ctx[i];
3266+
3267+
if ((GET_PIPE_SYNCD_FROM_PIPE(pipe_ctx_check) == disabled_master_pipe_idx) &&
3268+
IS_PIPE_SYNCD_VALID(pipe_ctx_check) && (i != disabled_master_pipe_idx))
3269+
DC_ERR("DC: Failure: pipe_idx[%d] syncd with disabled master pipe_idx[%d]\n",
3270+
i, disabled_master_pipe_idx);
3271+
}
3272+
}
3273+
32203274
uint8_t resource_transmitter_to_phy_idx(const struct dc *dc, enum transmitter transmitter)
32213275
{
32223276
/* TODO - get transmitter to phy idx mapping from DMUB */

‎drivers/gpu/drm/amd/display/dc/dc.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -344,6 +344,7 @@ struct dc_config {
344344
uint8_t vblank_alignment_max_frame_time_diff;
345345
bool is_asymmetric_memory;
346346
bool is_single_rank_dimm;
347+
bool use_pipe_ctx_sync_logic;
347348
};
348349

349350
enum visual_confirm {

‎drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

Lines changed: 9 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1566,6 +1566,10 @@ static enum dc_status apply_single_controller_ctx_to_hw(
15661566
&pipe_ctx->stream->audio_info);
15671567
}
15681568

1569+
/* make sure no pipes syncd to the pipe being enabled */
1570+
if (!pipe_ctx->stream->apply_seamless_boot_optimization && dc->config.use_pipe_ctx_sync_logic)
1571+
check_syncd_pipes_for_disabled_master_pipe(dc, context, pipe_ctx->pipe_idx);
1572+
15691573
#if defined(CONFIG_DRM_AMD_DC_DCN)
15701574
/* DCN3.1 FPGA Workaround
15711575
* Need to enable HPO DP Stream Encoder before setting OTG master enable.
@@ -1604,7 +1608,7 @@ static enum dc_status apply_single_controller_ctx_to_hw(
16041608
pipe_ctx->stream_res.stream_enc,
16051609
pipe_ctx->stream_res.tg->inst);
16061610

1607-
if (dc_is_dp_signal(pipe_ctx->stream->signal) &&
1611+
if (dc_is_embedded_signal(pipe_ctx->stream->signal) &&
16081612
pipe_ctx->stream_res.stream_enc->funcs->reset_fifo)
16091613
pipe_ctx->stream_res.stream_enc->funcs->reset_fifo(
16101614
pipe_ctx->stream_res.stream_enc);
@@ -2297,6 +2301,10 @@ enum dc_status dce110_apply_ctx_to_hw(
22972301
enum dc_status status;
22982302
int i;
22992303

2304+
/* reset syncd pipes from disabled pipes */
2305+
if (dc->config.use_pipe_ctx_sync_logic)
2306+
reset_syncd_pipes_from_disabled_pipes(dc, context);
2307+
23002308
/* Reset old context */
23012309
/* look up the targets that have been removed since last commit */
23022310
hws->funcs.reset_hw_ctx_wrap(dc, context);

‎drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1878,7 +1878,6 @@ noinline bool dcn30_internal_validate_bw(
18781878
dc->res_pool->funcs->update_soc_for_wm_a(dc, context);
18791879
pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate);
18801880

1881-
DC_FP_START();
18821881
if (!pipe_cnt) {
18831882
out = true;
18841883
goto validate_out;
@@ -2104,7 +2103,6 @@ noinline bool dcn30_internal_validate_bw(
21042103
out = false;
21052104

21062105
validate_out:
2107-
DC_FP_END();
21082106
return out;
21092107
}
21102108

@@ -2306,7 +2304,9 @@ bool dcn30_validate_bandwidth(struct dc *dc,
23062304

23072305
BW_VAL_TRACE_COUNT();
23082306

2307+
DC_FP_START();
23092308
out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate);
2309+
DC_FP_END();
23102310

23112311
if (pipe_cnt == 0)
23122312
goto validate_out;

‎drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c

Lines changed: 12 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -686,7 +686,7 @@ static const struct dc_debug_options debug_defaults_drv = {
686686
.disable_clock_gate = true,
687687
.disable_pplib_clock_request = true,
688688
.disable_pplib_wm_range = true,
689-
.pipe_split_policy = MPC_SPLIT_DYNAMIC,
689+
.pipe_split_policy = MPC_SPLIT_AVOID,
690690
.force_single_disp_pipe_split = false,
691691
.disable_dcc = DCC_ENABLE,
692692
.vsr_support = true,
@@ -1380,6 +1380,17 @@ static void set_wm_ranges(
13801380
pp_smu->nv_funcs.set_wm_ranges(&pp_smu->nv_funcs.pp_smu, &ranges);
13811381
}
13821382

1383+
static void dcn301_calculate_wm_and_dlg(
1384+
struct dc *dc, struct dc_state *context,
1385+
display_e2e_pipe_params_st *pipes,
1386+
int pipe_cnt,
1387+
int vlevel)
1388+
{
1389+
DC_FP_START();
1390+
dcn301_calculate_wm_and_dlg_fp(dc, context, pipes, pipe_cnt, vlevel);
1391+
DC_FP_END();
1392+
}
1393+
13831394
static struct resource_funcs dcn301_res_pool_funcs = {
13841395
.destroy = dcn301_destroy_resource_pool,
13851396
.link_enc_create = dcn301_link_encoder_create,

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