@@ -361,12 +361,42 @@ enum iommufd_hwpt_alloc_flags {
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IOMMU_HWPT_ALLOC_DIRTY_TRACKING = 1 << 1 ,
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};
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+ /**
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+ * enum iommu_hwpt_vtd_s1_flags - Intel VT-d stage-1 page table
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+ * entry attributes
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+ * @IOMMU_VTD_S1_SRE: Supervisor request
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+ * @IOMMU_VTD_S1_EAFE: Extended access enable
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+ * @IOMMU_VTD_S1_WPE: Write protect enable
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+ */
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+ enum iommu_hwpt_vtd_s1_flags {
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+ IOMMU_VTD_S1_SRE = 1 << 0 ,
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+ IOMMU_VTD_S1_EAFE = 1 << 1 ,
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+ IOMMU_VTD_S1_WPE = 1 << 2 ,
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+ };
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+
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+ /**
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+ * struct iommu_hwpt_vtd_s1 - Intel VT-d stage-1 page table
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+ * info (IOMMU_HWPT_DATA_VTD_S1)
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+ * @flags: Combination of enum iommu_hwpt_vtd_s1_flags
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+ * @pgtbl_addr: The base address of the stage-1 page table.
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+ * @addr_width: The address width of the stage-1 page table
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+ * @__reserved: Must be 0
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+ */
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+ struct iommu_hwpt_vtd_s1 {
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+ __aligned_u64 flags ;
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+ __aligned_u64 pgtbl_addr ;
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+ __u32 addr_width ;
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+ __u32 __reserved ;
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+ };
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+
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/**
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* enum iommu_hwpt_data_type - IOMMU HWPT Data Type
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* @IOMMU_HWPT_DATA_NONE: no data
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+ * @IOMMU_HWPT_DATA_VTD_S1: Intel VT-d stage-1 page table
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*/
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enum iommu_hwpt_data_type {
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IOMMU_HWPT_DATA_NONE ,
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+ IOMMU_HWPT_DATA_VTD_S1 ,
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};
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/**
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