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avpatelMarc Zyngier
avpatel
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Marc Zyngier
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genirq: Add mechanism to multiplex a single HW IPI
All RISC-V platforms have a single HW IPI provided by the INTC local interrupt controller. The HW method to trigger INTC IPI can be through external irqchip (e.g. RISC-V AIA), through platform specific device (e.g. SiFive CLINT timer), or through firmware (e.g. SBI IPI call). To support multiple IPIs on RISC-V, add a generic IPI multiplexing mechanism which help us create multiple virtual IPIs using a single HW IPI. This generic IPI multiplexing is inspired by the Apple AIC irqchip driver and it is shared by various RISC-V irqchip drivers. Signed-off-by: Anup Patel <[email protected]> Reviewed-by: Hector Martin <[email protected]> Tested-by: Hector Martin <[email protected]> Signed-off-by: Marc Zyngier <[email protected]> Link: https://lore.kernel.org/r/[email protected]
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‎include/linux/irq.h

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@@ -1266,6 +1266,9 @@ int __ipi_send_mask(struct irq_desc *desc, const struct cpumask *dest);
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int ipi_send_single(unsigned int virq, unsigned int cpu);
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int ipi_send_mask(unsigned int virq, const struct cpumask *dest);
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void ipi_mux_process(void);
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int ipi_mux_create(unsigned int nr_ipi, void (*mux_send)(unsigned int cpu));
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#ifdef CONFIG_GENERIC_IRQ_MULTI_HANDLER
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/*
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* Registers a generic IRQ handling function as the top-level IRQ handler in

‎kernel/irq/Kconfig

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@@ -86,6 +86,11 @@ config GENERIC_IRQ_IPI
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depends on SMP
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select IRQ_DOMAIN_HIERARCHY
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# Generic IRQ IPI Mux support
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config GENERIC_IRQ_IPI_MUX
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bool
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depends on SMP
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# Generic MSI hierarchical interrupt domain support
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config GENERIC_MSI_IRQ
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bool

‎kernel/irq/Makefile

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@@ -15,6 +15,7 @@ obj-$(CONFIG_GENERIC_IRQ_MIGRATION) += cpuhotplug.o
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obj-$(CONFIG_PM_SLEEP) += pm.o
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obj-$(CONFIG_GENERIC_MSI_IRQ) += msi.o
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obj-$(CONFIG_GENERIC_IRQ_IPI) += ipi.o
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obj-$(CONFIG_GENERIC_IRQ_IPI_MUX) += ipi-mux.o
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obj-$(CONFIG_SMP) += affinity.o
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obj-$(CONFIG_GENERIC_IRQ_DEBUGFS) += debugfs.o
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obj-$(CONFIG_GENERIC_IRQ_MATRIX_ALLOCATOR) += matrix.o

‎kernel/irq/ipi-mux.c

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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Multiplex several virtual IPIs over a single HW IPI.
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*
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* Copyright The Asahi Linux Contributors
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* Copyright (c) 2022 Ventana Micro Systems Inc.
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*/
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#define pr_fmt(fmt) "ipi-mux: " fmt
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#include <linux/cpu.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/irqchip.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/irqdomain.h>
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#include <linux/jump_label.h>
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#include <linux/percpu.h>
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#include <linux/smp.h>
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struct ipi_mux_cpu {
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atomic_t enable;
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atomic_t bits;
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};
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static struct ipi_mux_cpu __percpu *ipi_mux_pcpu;
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static struct irq_domain *ipi_mux_domain;
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static void (*ipi_mux_send)(unsigned int cpu);
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static void ipi_mux_mask(struct irq_data *d)
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{
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struct ipi_mux_cpu *icpu = this_cpu_ptr(ipi_mux_pcpu);
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atomic_andnot(BIT(irqd_to_hwirq(d)), &icpu->enable);
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}
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static void ipi_mux_unmask(struct irq_data *d)
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{
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struct ipi_mux_cpu *icpu = this_cpu_ptr(ipi_mux_pcpu);
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u32 ibit = BIT(irqd_to_hwirq(d));
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atomic_or(ibit, &icpu->enable);
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/*
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* The atomic_or() above must complete before the atomic_read()
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* below to avoid racing ipi_mux_send_mask().
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*/
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smp_mb__after_atomic();
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/* If a pending IPI was unmasked, raise a parent IPI immediately. */
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if (atomic_read(&icpu->bits) & ibit)
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ipi_mux_send(smp_processor_id());
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}
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static void ipi_mux_send_mask(struct irq_data *d, const struct cpumask *mask)
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{
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struct ipi_mux_cpu *icpu = this_cpu_ptr(ipi_mux_pcpu);
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u32 ibit = BIT(irqd_to_hwirq(d));
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unsigned long pending;
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int cpu;
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for_each_cpu(cpu, mask) {
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icpu = per_cpu_ptr(ipi_mux_pcpu, cpu);
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/*
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* This sequence is the mirror of the one in ipi_mux_unmask();
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* see the comment there. Additionally, release semantics
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* ensure that the vIPI flag set is ordered after any shared
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* memory accesses that precede it. This therefore also pairs
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* with the atomic_fetch_andnot in ipi_mux_process().
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*/
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pending = atomic_fetch_or_release(ibit, &icpu->bits);
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/*
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* The atomic_fetch_or_release() above must complete
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* before the atomic_read() below to avoid racing with
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* ipi_mux_unmask().
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*/
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smp_mb__after_atomic();
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/*
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* The flag writes must complete before the physical IPI is
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* issued to another CPU. This is implied by the control
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* dependency on the result of atomic_read() below, which is
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* itself already ordered after the vIPI flag write.
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*/
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if (!(pending & ibit) && (atomic_read(&icpu->enable) & ibit))
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ipi_mux_send(cpu);
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}
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}
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static const struct irq_chip ipi_mux_chip = {
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.name = "IPI Mux",
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.irq_mask = ipi_mux_mask,
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.irq_unmask = ipi_mux_unmask,
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.ipi_send_mask = ipi_mux_send_mask,
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};
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static int ipi_mux_domain_alloc(struct irq_domain *d, unsigned int virq,
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unsigned int nr_irqs, void *arg)
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{
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int i;
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for (i = 0; i < nr_irqs; i++) {
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irq_set_percpu_devid(virq + i);
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irq_domain_set_info(d, virq + i, i, &ipi_mux_chip, NULL,
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handle_percpu_devid_irq, NULL, NULL);
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}
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return 0;
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}
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static const struct irq_domain_ops ipi_mux_domain_ops = {
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.alloc = ipi_mux_domain_alloc,
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.free = irq_domain_free_irqs_top,
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};
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/**
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* ipi_mux_process - Process multiplexed virtual IPIs
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*/
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void ipi_mux_process(void)
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{
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struct ipi_mux_cpu *icpu = this_cpu_ptr(ipi_mux_pcpu);
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irq_hw_number_t hwirq;
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unsigned long ipis;
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unsigned int en;
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/*
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* Reading enable mask does not need to be ordered as long as
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* this function is called from interrupt handler because only
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* the CPU itself can change it's own enable mask.
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*/
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en = atomic_read(&icpu->enable);
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/*
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* Clear the IPIs we are about to handle. This pairs with the
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* atomic_fetch_or_release() in ipi_mux_send_mask().
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*/
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ipis = atomic_fetch_andnot(en, &icpu->bits) & en;
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for_each_set_bit(hwirq, &ipis, BITS_PER_TYPE(int))
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generic_handle_domain_irq(ipi_mux_domain, hwirq);
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}
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/**
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* ipi_mux_create - Create virtual IPIs multiplexed on top of a single
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* parent IPI.
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* @nr_ipi: number of virtual IPIs to create. This should
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* be <= BITS_PER_TYPE(int)
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* @mux_send: callback to trigger parent IPI for a particular CPU
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*
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* Returns first virq of the newly created virtual IPIs upon success
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* or <=0 upon failure
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*/
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int ipi_mux_create(unsigned int nr_ipi, void (*mux_send)(unsigned int cpu))
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{
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struct fwnode_handle *fwnode;
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struct irq_domain *domain;
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int rc;
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if (ipi_mux_domain)
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return -EEXIST;
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if (BITS_PER_TYPE(int) < nr_ipi || !mux_send)
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return -EINVAL;
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ipi_mux_pcpu = alloc_percpu(typeof(*ipi_mux_pcpu));
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if (!ipi_mux_pcpu)
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return -ENOMEM;
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fwnode = irq_domain_alloc_named_fwnode("IPI-Mux");
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if (!fwnode) {
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pr_err("unable to create IPI Mux fwnode\n");
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rc = -ENOMEM;
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goto fail_free_cpu;
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}
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domain = irq_domain_create_linear(fwnode, nr_ipi,
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&ipi_mux_domain_ops, NULL);
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if (!domain) {
180+
pr_err("unable to add IPI Mux domain\n");
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rc = -ENOMEM;
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goto fail_free_fwnode;
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}
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domain->flags |= IRQ_DOMAIN_FLAG_IPI_SINGLE;
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irq_domain_update_bus_token(domain, DOMAIN_BUS_IPI);
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rc = __irq_domain_alloc_irqs(domain, -1, nr_ipi,
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NUMA_NO_NODE, NULL, false, NULL);
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if (rc <= 0) {
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pr_err("unable to alloc IRQs from IPI Mux domain\n");
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goto fail_free_domain;
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}
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ipi_mux_domain = domain;
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ipi_mux_send = mux_send;
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return rc;
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fail_free_domain:
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irq_domain_remove(domain);
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fail_free_fwnode:
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irq_domain_free_fwnode(fwnode);
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fail_free_cpu:
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free_percpu(ipi_mux_pcpu);
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return rc;
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}

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