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jnikulajnikula
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drm/i915/vrr: convert to struct intel_display
Going forward, struct intel_display shall replace struct drm_i915_private as the main display device data pointer type. Convert intel_vrr.[ch] to struct intel_display. Reviewed-by: Rodrigo Vivi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/1d25a08c62a320133fbb0a89dac3dd1081139487.1724342644.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <[email protected]>
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‎drivers/gpu/drm/i915/display/intel_vrr.c

Lines changed: 61 additions & 66 deletions
Original file line numberDiff line numberDiff line change
@@ -17,8 +17,8 @@
1717

1818
bool intel_vrr_is_capable(struct intel_connector *connector)
1919
{
20+
struct intel_display *display = to_intel_display(connector);
2021
const struct drm_display_info *info = &connector->base.display_info;
21-
struct drm_i915_private *i915 = to_i915(connector->base.dev);
2222
struct intel_dp *intel_dp;
2323

2424
/*
@@ -43,7 +43,7 @@ bool intel_vrr_is_capable(struct intel_connector *connector)
4343
return false;
4444
}
4545

46-
return HAS_VRR(i915) &&
46+
return HAS_VRR(display) &&
4747
info->monitor_range.max_vfreq - info->monitor_range.min_vfreq > 10;
4848
}
4949

@@ -89,10 +89,9 @@ intel_vrr_check_modeset(struct intel_atomic_state *state)
8989
*/
9090
static int intel_vrr_vblank_exit_length(const struct intel_crtc_state *crtc_state)
9191
{
92-
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
93-
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
92+
struct intel_display *display = to_intel_display(crtc_state);
9493

95-
if (DISPLAY_VER(i915) >= 13)
94+
if (DISPLAY_VER(display) >= 13)
9695
return crtc_state->vrr.guardband;
9796
else
9897
/* The hw imposes the extra scanline before frame start */
@@ -113,11 +112,11 @@ int intel_vrr_vmax_vblank_start(const struct intel_crtc_state *crtc_state)
113112
static bool
114113
is_cmrr_frac_required(struct intel_crtc_state *crtc_state)
115114
{
115+
struct intel_display *display = to_intel_display(crtc_state);
116116
int calculated_refresh_k, actual_refresh_k, pixel_clock_per_line;
117117
struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
118-
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
119118

120-
if (!HAS_CMRR(i915))
119+
if (!HAS_CMRR(display))
121120
return false;
122121

123122
actual_refresh_k =
@@ -161,8 +160,7 @@ void
161160
intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
162161
struct drm_connector_state *conn_state)
163162
{
164-
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
165-
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
163+
struct intel_display *display = to_intel_display(crtc_state);
166164
struct intel_connector *connector =
167165
to_intel_connector(conn_state->connector);
168166
struct intel_dp *intel_dp = intel_attached_dp(connector);
@@ -186,7 +184,7 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
186184
if (!crtc_state->vrr.in_range)
187185
return;
188186

189-
if (HAS_LRR(i915))
187+
if (HAS_LRR(display))
190188
crtc_state->update_lrr = true;
191189

192190
vmin = DIV_ROUND_UP(adjusted_mode->crtc_clock * 1000,
@@ -246,7 +244,7 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
246244
* For XE_LPD+, we use guardband and pipeline override
247245
* is deprecated.
248246
*/
249-
if (DISPLAY_VER(i915) >= 13) {
247+
if (DISPLAY_VER(display) >= 13) {
250248
crtc_state->vrr.guardband =
251249
crtc_state->vrr.vmin + 1 - adjusted_mode->crtc_vblank_start;
252250
} else {
@@ -258,9 +256,9 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
258256

259257
static u32 trans_vrr_ctl(const struct intel_crtc_state *crtc_state)
260258
{
261-
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
259+
struct intel_display *display = to_intel_display(crtc_state);
262260

263-
if (DISPLAY_VER(i915) >= 13)
261+
if (DISPLAY_VER(display) >= 13)
264262
return VRR_CTL_IGN_MAX_SHIFT | VRR_CTL_FLIP_LINE_EN |
265263
XELPD_VRR_CTL_VRR_GUARDBAND(crtc_state->vrr.guardband);
266264
else
@@ -271,141 +269,138 @@ static u32 trans_vrr_ctl(const struct intel_crtc_state *crtc_state)
271269

272270
void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
273271
{
274-
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
272+
struct intel_display *display = to_intel_display(crtc_state);
275273
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
276274

277275
/*
278276
* This bit seems to have two meanings depending on the platform:
279277
* TGL: generate VRR "safe window" for DSB vblank waits
280278
* ADL/DG2: make TRANS_SET_CONTEXT_LATENCY effective with VRR
281279
*/
282-
if (IS_DISPLAY_VER(dev_priv, 12, 13))
283-
intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder),
280+
if (IS_DISPLAY_VER(display, 12, 13))
281+
intel_de_rmw(display, CHICKEN_TRANS(cpu_transcoder),
284282
0, PIPE_VBLANK_WITH_DELAY);
285283

286284
if (!crtc_state->vrr.flipline) {
287-
intel_de_write(dev_priv,
288-
TRANS_VRR_CTL(dev_priv, cpu_transcoder), 0);
285+
intel_de_write(display,
286+
TRANS_VRR_CTL(display, cpu_transcoder), 0);
289287
return;
290288
}
291289

292290
if (crtc_state->cmrr.enable) {
293-
intel_de_write(dev_priv, TRANS_CMRR_M_HI(dev_priv, cpu_transcoder),
291+
intel_de_write(display, TRANS_CMRR_M_HI(display, cpu_transcoder),
294292
upper_32_bits(crtc_state->cmrr.cmrr_m));
295-
intel_de_write(dev_priv, TRANS_CMRR_M_LO(dev_priv, cpu_transcoder),
293+
intel_de_write(display, TRANS_CMRR_M_LO(display, cpu_transcoder),
296294
lower_32_bits(crtc_state->cmrr.cmrr_m));
297-
intel_de_write(dev_priv, TRANS_CMRR_N_HI(dev_priv, cpu_transcoder),
295+
intel_de_write(display, TRANS_CMRR_N_HI(display, cpu_transcoder),
298296
upper_32_bits(crtc_state->cmrr.cmrr_n));
299-
intel_de_write(dev_priv, TRANS_CMRR_N_LO(dev_priv, cpu_transcoder),
297+
intel_de_write(display, TRANS_CMRR_N_LO(display, cpu_transcoder),
300298
lower_32_bits(crtc_state->cmrr.cmrr_n));
301299
}
302300

303-
intel_de_write(dev_priv, TRANS_VRR_VMIN(dev_priv, cpu_transcoder),
301+
intel_de_write(display, TRANS_VRR_VMIN(display, cpu_transcoder),
304302
crtc_state->vrr.vmin - 1);
305-
intel_de_write(dev_priv, TRANS_VRR_VMAX(dev_priv, cpu_transcoder),
303+
intel_de_write(display, TRANS_VRR_VMAX(display, cpu_transcoder),
306304
crtc_state->vrr.vmax - 1);
307-
intel_de_write(dev_priv, TRANS_VRR_CTL(dev_priv, cpu_transcoder),
305+
intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
308306
trans_vrr_ctl(crtc_state));
309-
intel_de_write(dev_priv, TRANS_VRR_FLIPLINE(dev_priv, cpu_transcoder),
307+
intel_de_write(display, TRANS_VRR_FLIPLINE(display, cpu_transcoder),
310308
crtc_state->vrr.flipline - 1);
311309
}
312310

313311
void intel_vrr_send_push(const struct intel_crtc_state *crtc_state)
314312
{
315-
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
316-
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
313+
struct intel_display *display = to_intel_display(crtc_state);
317314
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
318315

319316
if (!crtc_state->vrr.enable)
320317
return;
321318

322-
intel_de_write(dev_priv, TRANS_PUSH(dev_priv, cpu_transcoder),
319+
intel_de_write(display, TRANS_PUSH(display, cpu_transcoder),
323320
TRANS_PUSH_EN | TRANS_PUSH_SEND);
324321
}
325322

326323
bool intel_vrr_is_push_sent(const struct intel_crtc_state *crtc_state)
327324
{
328-
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
329-
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
325+
struct intel_display *display = to_intel_display(crtc_state);
330326
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
331327

332328
if (!crtc_state->vrr.enable)
333329
return false;
334330

335-
return intel_de_read(dev_priv, TRANS_PUSH(dev_priv, cpu_transcoder)) & TRANS_PUSH_SEND;
331+
return intel_de_read(display, TRANS_PUSH(display, cpu_transcoder)) & TRANS_PUSH_SEND;
336332
}
337333

338334
void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
339335
{
340-
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
336+
struct intel_display *display = to_intel_display(crtc_state);
341337
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
342338

343339
if (!crtc_state->vrr.enable)
344340
return;
345341

346-
intel_de_write(dev_priv, TRANS_PUSH(dev_priv, cpu_transcoder),
342+
intel_de_write(display, TRANS_PUSH(display, cpu_transcoder),
347343
TRANS_PUSH_EN);
348344

349-
if (HAS_AS_SDP(dev_priv))
350-
intel_de_write(dev_priv,
351-
TRANS_VRR_VSYNC(dev_priv, cpu_transcoder),
345+
if (HAS_AS_SDP(display))
346+
intel_de_write(display,
347+
TRANS_VRR_VSYNC(display, cpu_transcoder),
352348
VRR_VSYNC_END(crtc_state->vrr.vsync_end) |
353349
VRR_VSYNC_START(crtc_state->vrr.vsync_start));
354350

355351
if (crtc_state->cmrr.enable) {
356-
intel_de_write(dev_priv, TRANS_VRR_CTL(dev_priv, cpu_transcoder),
352+
intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
357353
VRR_CTL_VRR_ENABLE | VRR_CTL_CMRR_ENABLE |
358354
trans_vrr_ctl(crtc_state));
359355
} else {
360-
intel_de_write(dev_priv, TRANS_VRR_CTL(dev_priv, cpu_transcoder),
356+
intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
361357
VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state));
362358
}
363359
}
364360

365361
void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
366362
{
367-
struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
368-
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
363+
struct intel_display *display = to_intel_display(old_crtc_state);
369364
enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
370365

371366
if (!old_crtc_state->vrr.enable)
372367
return;
373368

374-
intel_de_write(dev_priv, TRANS_VRR_CTL(dev_priv, cpu_transcoder),
369+
intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
375370
trans_vrr_ctl(old_crtc_state));
376-
intel_de_wait_for_clear(dev_priv,
377-
TRANS_VRR_STATUS(dev_priv, cpu_transcoder),
371+
intel_de_wait_for_clear(display,
372+
TRANS_VRR_STATUS(display, cpu_transcoder),
378373
VRR_STATUS_VRR_EN_LIVE, 1000);
379-
intel_de_write(dev_priv, TRANS_PUSH(dev_priv, cpu_transcoder), 0);
374+
intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), 0);
380375

381-
if (HAS_AS_SDP(dev_priv))
382-
intel_de_write(dev_priv,
383-
TRANS_VRR_VSYNC(dev_priv, cpu_transcoder), 0);
376+
if (HAS_AS_SDP(display))
377+
intel_de_write(display,
378+
TRANS_VRR_VSYNC(display, cpu_transcoder), 0);
384379
}
385380

386381
void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
387382
{
388-
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
383+
struct intel_display *display = to_intel_display(crtc_state);
389384
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
390385
u32 trans_vrr_ctl, trans_vrr_vsync;
391386

392-
trans_vrr_ctl = intel_de_read(dev_priv,
393-
TRANS_VRR_CTL(dev_priv, cpu_transcoder));
387+
trans_vrr_ctl = intel_de_read(display,
388+
TRANS_VRR_CTL(display, cpu_transcoder));
394389

395390
crtc_state->vrr.enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE;
396-
if (HAS_CMRR(dev_priv))
391+
if (HAS_CMRR(display))
397392
crtc_state->cmrr.enable = (trans_vrr_ctl & VRR_CTL_CMRR_ENABLE);
398393

399394
if (crtc_state->cmrr.enable) {
400395
crtc_state->cmrr.cmrr_n =
401-
intel_de_read64_2x32(dev_priv, TRANS_CMRR_N_LO(dev_priv, cpu_transcoder),
402-
TRANS_CMRR_N_HI(dev_priv, cpu_transcoder));
396+
intel_de_read64_2x32(display, TRANS_CMRR_N_LO(display, cpu_transcoder),
397+
TRANS_CMRR_N_HI(display, cpu_transcoder));
403398
crtc_state->cmrr.cmrr_m =
404-
intel_de_read64_2x32(dev_priv, TRANS_CMRR_M_LO(dev_priv, cpu_transcoder),
405-
TRANS_CMRR_M_HI(dev_priv, cpu_transcoder));
399+
intel_de_read64_2x32(display, TRANS_CMRR_M_LO(display, cpu_transcoder),
400+
TRANS_CMRR_M_HI(display, cpu_transcoder));
406401
}
407402

408-
if (DISPLAY_VER(dev_priv) >= 13)
403+
if (DISPLAY_VER(display) >= 13)
409404
crtc_state->vrr.guardband =
410405
REG_FIELD_GET(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, trans_vrr_ctl);
411406
else
@@ -414,21 +409,21 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
414409
REG_FIELD_GET(VRR_CTL_PIPELINE_FULL_MASK, trans_vrr_ctl);
415410

416411
if (trans_vrr_ctl & VRR_CTL_FLIP_LINE_EN) {
417-
crtc_state->vrr.flipline = intel_de_read(dev_priv,
418-
TRANS_VRR_FLIPLINE(dev_priv, cpu_transcoder)) + 1;
419-
crtc_state->vrr.vmax = intel_de_read(dev_priv,
420-
TRANS_VRR_VMAX(dev_priv, cpu_transcoder)) + 1;
421-
crtc_state->vrr.vmin = intel_de_read(dev_priv,
422-
TRANS_VRR_VMIN(dev_priv, cpu_transcoder)) + 1;
412+
crtc_state->vrr.flipline = intel_de_read(display,
413+
TRANS_VRR_FLIPLINE(display, cpu_transcoder)) + 1;
414+
crtc_state->vrr.vmax = intel_de_read(display,
415+
TRANS_VRR_VMAX(display, cpu_transcoder)) + 1;
416+
crtc_state->vrr.vmin = intel_de_read(display,
417+
TRANS_VRR_VMIN(display, cpu_transcoder)) + 1;
423418
}
424419

425420
if (crtc_state->vrr.enable) {
426421
crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
427422

428-
if (HAS_AS_SDP(dev_priv)) {
423+
if (HAS_AS_SDP(display)) {
429424
trans_vrr_vsync =
430-
intel_de_read(dev_priv,
431-
TRANS_VRR_VSYNC(dev_priv, cpu_transcoder));
425+
intel_de_read(display,
426+
TRANS_VRR_VSYNC(display, cpu_transcoder));
432427
crtc_state->vrr.vsync_start =
433428
REG_FIELD_GET(VRR_VSYNC_START_MASK, trans_vrr_vsync);
434429
crtc_state->vrr.vsync_end =

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