@@ -525,6 +525,7 @@ static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
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struct smu_11_0_dpm_context * dpm_context = smu -> smu_dpm .dpm_context ;
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PPTable_t * driver_ppt = smu -> smu_table .driver_pptable ;
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struct smu_11_0_dpm_table * dpm_table ;
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+ struct amdgpu_device * adev = smu -> adev ;
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int ret = 0 ;
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/* socclk dpm table setup */
@@ -618,21 +619,24 @@ static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
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}
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/* vclk1 dpm table setup */
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- dpm_table = & dpm_context -> dpm_tables .vclk1_table ;
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- if (smu_cmn_feature_is_enabled (smu , SMU_FEATURE_MM_DPM_PG_BIT )) {
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- ret = smu_v11_0_set_single_dpm_table (smu ,
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- SMU_VCLK1 ,
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- dpm_table );
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- if (ret )
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- return ret ;
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- dpm_table -> is_fine_grained =
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- !driver_ppt -> DpmDescriptor [PPCLK_VCLK_1 ].SnapToDiscrete ;
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- } else {
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- dpm_table -> count = 1 ;
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- dpm_table -> dpm_levels [0 ].value = smu -> smu_table .boot_values .vclk / 100 ;
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- dpm_table -> dpm_levels [0 ].enabled = true;
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- dpm_table -> min = dpm_table -> dpm_levels [0 ].value ;
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- dpm_table -> max = dpm_table -> dpm_levels [0 ].value ;
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+ if (adev -> vcn .num_vcn_inst > 1 ) {
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+ dpm_table = & dpm_context -> dpm_tables .vclk1_table ;
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+ if (smu_cmn_feature_is_enabled (smu , SMU_FEATURE_MM_DPM_PG_BIT )) {
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+ ret = smu_v11_0_set_single_dpm_table (smu ,
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+ SMU_VCLK1 ,
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+ dpm_table );
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+ if (ret )
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+ return ret ;
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+ dpm_table -> is_fine_grained =
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+ !driver_ppt -> DpmDescriptor [PPCLK_VCLK_1 ].SnapToDiscrete ;
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+ } else {
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+ dpm_table -> count = 1 ;
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+ dpm_table -> dpm_levels [0 ].value =
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+ smu -> smu_table .boot_values .vclk / 100 ;
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+ dpm_table -> dpm_levels [0 ].enabled = true;
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+ dpm_table -> min = dpm_table -> dpm_levels [0 ].value ;
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+ dpm_table -> max = dpm_table -> dpm_levels [0 ].value ;
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+ }
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}
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/* dclk0 dpm table setup */
@@ -654,21 +658,24 @@ static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
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}
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/* dclk1 dpm table setup */
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- dpm_table = & dpm_context -> dpm_tables .dclk1_table ;
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- if (smu_cmn_feature_is_enabled (smu , SMU_FEATURE_MM_DPM_PG_BIT )) {
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- ret = smu_v11_0_set_single_dpm_table (smu ,
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- SMU_DCLK1 ,
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- dpm_table );
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- if (ret )
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- return ret ;
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- dpm_table -> is_fine_grained =
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- !driver_ppt -> DpmDescriptor [PPCLK_DCLK_1 ].SnapToDiscrete ;
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- } else {
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- dpm_table -> count = 1 ;
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- dpm_table -> dpm_levels [0 ].value = smu -> smu_table .boot_values .dclk / 100 ;
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- dpm_table -> dpm_levels [0 ].enabled = true;
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- dpm_table -> min = dpm_table -> dpm_levels [0 ].value ;
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- dpm_table -> max = dpm_table -> dpm_levels [0 ].value ;
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+ if (adev -> vcn .num_vcn_inst > 1 ) {
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+ dpm_table = & dpm_context -> dpm_tables .dclk1_table ;
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+ if (smu_cmn_feature_is_enabled (smu , SMU_FEATURE_MM_DPM_PG_BIT )) {
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+ ret = smu_v11_0_set_single_dpm_table (smu ,
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+ SMU_DCLK1 ,
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+ dpm_table );
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+ if (ret )
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+ return ret ;
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+ dpm_table -> is_fine_grained =
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+ !driver_ppt -> DpmDescriptor [PPCLK_DCLK_1 ].SnapToDiscrete ;
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+ } else {
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+ dpm_table -> count = 1 ;
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+ dpm_table -> dpm_levels [0 ].value =
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+ smu -> smu_table .boot_values .dclk / 100 ;
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+ dpm_table -> dpm_levels [0 ].enabled = true;
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+ dpm_table -> min = dpm_table -> dpm_levels [0 ].value ;
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+ dpm_table -> max = dpm_table -> dpm_levels [0 ].value ;
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+ }
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}
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/* dcefclk dpm table setup */
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