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34 | 34 | #define GP_FIFO_BASE ((hrt_address)0x0000000000090104) /* This is NOT a base address */
|
35 | 35 |
|
36 | 36 | /* ISP */
|
37 |
| -static const hrt_address ISP_CTRL_BASE[N_ISP_ID] = { |
38 |
| - 0x0000000000020000ULL |
39 |
| -}; |
40 |
| - |
41 |
| -static const hrt_address ISP_DMEM_BASE[N_ISP_ID] = { |
42 |
| - 0x0000000000200000ULL |
43 |
| -}; |
44 |
| - |
45 |
| -static const hrt_address ISP_BAMEM_BASE[N_BAMEM_ID] = { |
46 |
| - 0x0000000000100000ULL |
47 |
| -}; |
| 37 | +extern const hrt_address ISP_CTRL_BASE[N_ISP_ID]; |
| 38 | +extern const hrt_address ISP_DMEM_BASE[N_ISP_ID]; |
| 39 | +extern const hrt_address ISP_BAMEM_BASE[N_BAMEM_ID]; |
48 | 40 |
|
49 | 41 | /* SP */
|
50 |
| -static const hrt_address SP_CTRL_BASE[N_SP_ID] = { |
51 |
| - 0x0000000000010000ULL |
52 |
| -}; |
53 |
| - |
54 |
| -static const hrt_address SP_DMEM_BASE[N_SP_ID] = { |
55 |
| - 0x0000000000300000ULL |
56 |
| -}; |
| 42 | +extern const hrt_address SP_CTRL_BASE[N_SP_ID]; |
| 43 | +extern const hrt_address SP_DMEM_BASE[N_SP_ID]; |
57 | 44 |
|
58 | 45 | /* MMU */
|
59 |
| -/* |
60 |
| - * MMU0_ID: The data MMU |
61 |
| - * MMU1_ID: The icache MMU |
62 |
| - */ |
63 |
| -static const hrt_address MMU_BASE[N_MMU_ID] = { |
64 |
| - 0x0000000000070000ULL, |
65 |
| - 0x00000000000A0000ULL |
66 |
| -}; |
67 | 46 |
|
68 |
| -/* DMA */ |
69 |
| -static const hrt_address DMA_BASE[N_DMA_ID] = { |
70 |
| - 0x0000000000040000ULL |
71 |
| -}; |
| 47 | +extern const hrt_address MMU_BASE[N_MMU_ID]; |
72 | 48 |
|
73 |
| -static const hrt_address ISYS2401_DMA_BASE[N_ISYS2401_DMA_ID] = { |
74 |
| - 0x00000000000CA000ULL |
75 |
| -}; |
| 49 | +/* DMA */ |
| 50 | +extern const hrt_address DMA_BASE[N_DMA_ID]; |
| 51 | +extern const hrt_address ISYS2401_DMA_BASE[N_ISYS2401_DMA_ID]; |
76 | 52 |
|
77 | 53 | /* IRQ */
|
78 |
| -static const hrt_address IRQ_BASE[N_IRQ_ID] = { |
79 |
| - 0x0000000000000500ULL, |
80 |
| - 0x0000000000030A00ULL, |
81 |
| - 0x000000000008C000ULL, |
82 |
| - 0x0000000000090200ULL |
83 |
| -}; |
84 |
| - |
85 |
| -/* |
86 |
| - 0x0000000000000500ULL}; |
87 |
| - */ |
| 54 | +extern const hrt_address IRQ_BASE[N_IRQ_ID]; |
88 | 55 |
|
89 | 56 | /* GDC */
|
90 |
| -static const hrt_address GDC_BASE[N_GDC_ID] = { |
91 |
| - 0x0000000000050000ULL, |
92 |
| - 0x0000000000060000ULL |
93 |
| -}; |
| 57 | +extern const hrt_address GDC_BASE[N_GDC_ID]; |
94 | 58 |
|
95 | 59 | /* FIFO_MONITOR (not a subset of GP_DEVICE) */
|
96 |
| -static const hrt_address FIFO_MONITOR_BASE[N_FIFO_MONITOR_ID] = { |
97 |
| - 0x0000000000000000ULL |
98 |
| -}; |
99 |
| - |
100 |
| -/* |
101 |
| -static const hrt_address GP_REGS_BASE[N_GP_REGS_ID] = { |
102 |
| - 0x0000000000000000ULL}; |
103 |
| -
|
104 |
| -static const hrt_address GP_DEVICE_BASE[N_GP_DEVICE_ID] = { |
105 |
| - 0x0000000000090000ULL}; |
106 |
| -*/ |
| 60 | +extern const hrt_address FIFO_MONITOR_BASE[N_FIFO_MONITOR_ID]; |
107 | 61 |
|
108 | 62 | /* GP_DEVICE (single base for all separate GP_REG instances) */
|
109 |
| -static const hrt_address GP_DEVICE_BASE[N_GP_DEVICE_ID] = { |
110 |
| - 0x0000000000000000ULL |
111 |
| -}; |
| 63 | +extern const hrt_address GP_DEVICE_BASE[N_GP_DEVICE_ID]; |
112 | 64 |
|
113 | 65 | /*GP TIMER , all timer registers are inter-twined,
|
114 | 66 | * so, having multiple base addresses for
|
115 | 67 | * different timers does not help*/
|
116 |
| -static const hrt_address GP_TIMER_BASE = |
117 |
| - (hrt_address)0x0000000000000600ULL; |
| 68 | +extern const hrt_address GP_TIMER_BASE; |
118 | 69 |
|
119 | 70 | /* GPIO */
|
120 |
| -static const hrt_address GPIO_BASE[N_GPIO_ID] = { |
121 |
| - 0x0000000000000400ULL |
122 |
| -}; |
| 71 | +extern const hrt_address GPIO_BASE[N_GPIO_ID]; |
123 | 72 |
|
124 | 73 | /* TIMED_CTRL */
|
125 |
| -static const hrt_address TIMED_CTRL_BASE[N_TIMED_CTRL_ID] = { |
126 |
| - 0x0000000000000100ULL |
127 |
| -}; |
| 74 | +extern const hrt_address TIMED_CTRL_BASE[N_TIMED_CTRL_ID]; |
128 | 75 |
|
129 | 76 | /* INPUT_FORMATTER */
|
130 |
| -static const hrt_address INPUT_FORMATTER_BASE[N_INPUT_FORMATTER_ID] = { |
131 |
| - 0x0000000000030000ULL, |
132 |
| - 0x0000000000030200ULL, |
133 |
| - 0x0000000000030400ULL, |
134 |
| - 0x0000000000030600ULL |
135 |
| -}; /* memcpy() */ |
| 77 | +extern const hrt_address INPUT_FORMATTER_BASE[N_INPUT_FORMATTER_ID]; |
136 | 78 |
|
137 | 79 | /* INPUT_SYSTEM */
|
138 |
| -static const hrt_address INPUT_SYSTEM_BASE[N_INPUT_SYSTEM_ID] = { |
139 |
| - 0x0000000000080000ULL |
140 |
| -}; |
141 |
| - |
142 |
| -/* 0x0000000000081000ULL, */ /* capture A */ |
143 |
| -/* 0x0000000000082000ULL, */ /* capture B */ |
144 |
| -/* 0x0000000000083000ULL, */ /* capture C */ |
145 |
| -/* 0x0000000000084000ULL, */ /* Acquisition */ |
146 |
| -/* 0x0000000000085000ULL, */ /* DMA */ |
147 |
| -/* 0x0000000000089000ULL, */ /* ctrl */ |
148 |
| -/* 0x000000000008A000ULL, */ /* GP regs */ |
149 |
| -/* 0x000000000008B000ULL, */ /* FIFO */ |
150 |
| -/* 0x000000000008C000ULL, */ /* IRQ */ |
| 80 | +extern const hrt_address INPUT_SYSTEM_BASE[N_INPUT_SYSTEM_ID]; |
151 | 81 |
|
152 | 82 | /* RX, the MIPI lane control regs start at offset 0 */
|
153 |
| -static const hrt_address RX_BASE[N_RX_ID] = { |
154 |
| - 0x0000000000080100ULL |
155 |
| -}; |
| 83 | +extern const hrt_address RX_BASE[N_RX_ID]; |
156 | 84 |
|
157 | 85 | /* IBUF_CTRL, part of the Input System 2401 */
|
158 |
| -static const hrt_address IBUF_CTRL_BASE[N_IBUF_CTRL_ID] = { |
159 |
| - 0x00000000000C1800ULL, /* ibuf controller A */ |
160 |
| - 0x00000000000C3800ULL, /* ibuf controller B */ |
161 |
| - 0x00000000000C5800ULL /* ibuf controller C */ |
162 |
| -}; |
| 86 | +extern const hrt_address IBUF_CTRL_BASE[N_IBUF_CTRL_ID]; |
163 | 87 |
|
164 | 88 | /* ISYS IRQ Controllers, part of the Input System 2401 */
|
165 |
| -static const hrt_address ISYS_IRQ_BASE[N_ISYS_IRQ_ID] = { |
166 |
| - 0x00000000000C1400ULL, /* port a */ |
167 |
| - 0x00000000000C3400ULL, /* port b */ |
168 |
| - 0x00000000000C5400ULL /* port c */ |
169 |
| -}; |
| 89 | +extern const hrt_address ISYS_IRQ_BASE[N_ISYS_IRQ_ID]; |
170 | 90 |
|
171 | 91 | /* CSI FE, part of the Input System 2401 */
|
172 |
| -static const hrt_address CSI_RX_FE_CTRL_BASE[N_CSI_RX_FRONTEND_ID] = { |
173 |
| - 0x00000000000C0400ULL, /* csi fe controller A */ |
174 |
| - 0x00000000000C2400ULL, /* csi fe controller B */ |
175 |
| - 0x00000000000C4400ULL /* csi fe controller C */ |
176 |
| -}; |
| 92 | +extern const hrt_address CSI_RX_FE_CTRL_BASE[N_CSI_RX_FRONTEND_ID]; |
177 | 93 |
|
178 | 94 | /* CSI BE, part of the Input System 2401 */
|
179 |
| -static const hrt_address CSI_RX_BE_CTRL_BASE[N_CSI_RX_BACKEND_ID] = { |
180 |
| - 0x00000000000C0800ULL, /* csi be controller A */ |
181 |
| - 0x00000000000C2800ULL, /* csi be controller B */ |
182 |
| - 0x00000000000C4800ULL /* csi be controller C */ |
183 |
| -}; |
| 95 | +extern const hrt_address CSI_RX_BE_CTRL_BASE[N_CSI_RX_BACKEND_ID]; |
184 | 96 |
|
185 | 97 | /* PIXEL Generator, part of the Input System 2401 */
|
186 |
| -static const hrt_address PIXELGEN_CTRL_BASE[N_PIXELGEN_ID] = { |
187 |
| - 0x00000000000C1000ULL, /* pixel gen controller A */ |
188 |
| - 0x00000000000C3000ULL, /* pixel gen controller B */ |
189 |
| - 0x00000000000C5000ULL /* pixel gen controller C */ |
190 |
| -}; |
| 98 | +extern const hrt_address PIXELGEN_CTRL_BASE[N_PIXELGEN_ID]; |
191 | 99 |
|
192 | 100 | /* Stream2MMIO, part of the Input System 2401 */
|
193 |
| -static const hrt_address STREAM2MMIO_CTRL_BASE[N_STREAM2MMIO_ID] = { |
194 |
| - 0x00000000000C0C00ULL, /* stream2mmio controller A */ |
195 |
| - 0x00000000000C2C00ULL, /* stream2mmio controller B */ |
196 |
| - 0x00000000000C4C00ULL /* stream2mmio controller C */ |
197 |
| -}; |
| 101 | +extern const hrt_address STREAM2MMIO_CTRL_BASE[N_STREAM2MMIO_ID]; |
198 | 102 |
|
199 | 103 | #endif /* __SYSTEM_LOCAL_H_INCLUDED__ */
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