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#define INSN_MATCH_C_FSWSP 0xe002
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#define INSN_MASK_C_FSWSP 0xe003
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+ #define INSN_MATCH_C_LHU 0x8400
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+ #define INSN_MASK_C_LHU 0xfc43
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+ #define INSN_MATCH_C_LH 0x8440
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+ #define INSN_MASK_C_LH 0xfc43
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+ #define INSN_MATCH_C_SH 0x8c00
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+ #define INSN_MASK_C_SH 0xfc43
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+
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#define INSN_LEN (insn ) ((((insn) & 0x3) < 0x3) ? 2 : 4)
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#if defined(CONFIG_64BIT )
@@ -431,6 +438,13 @@ static int handle_scalar_misaligned_load(struct pt_regs *regs)
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fp = 1 ;
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len = 4 ;
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#endif
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+ } else if ((insn & INSN_MASK_C_LHU ) == INSN_MATCH_C_LHU ) {
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+ len = 2 ;
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+ insn = RVC_RS2S (insn ) << SH_RD ;
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+ } else if ((insn & INSN_MASK_C_LH ) == INSN_MATCH_C_LH ) {
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+ len = 2 ;
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+ shift = 8 * (sizeof (ulong ) - len );
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+ insn = RVC_RS2S (insn ) << SH_RD ;
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} else {
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regs -> epc = epc ;
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return -1 ;
@@ -441,7 +455,7 @@ static int handle_scalar_misaligned_load(struct pt_regs *regs)
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val .data_u64 = 0 ;
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if (user_mode (regs )) {
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- if (copy_from_user (& val , (u8 __user * )addr , len ))
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+ if (copy_from_user_nofault (& val , (u8 __user * )addr , len ))
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return -1 ;
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} else {
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memcpy (& val , (u8 * )addr , len );
@@ -530,6 +544,9 @@ static int handle_scalar_misaligned_store(struct pt_regs *regs)
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len = 4 ;
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val .data_ulong = GET_F32_RS2C (insn , regs );
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#endif
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+ } else if ((insn & INSN_MASK_C_SH ) == INSN_MATCH_C_SH ) {
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+ len = 2 ;
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+ val .data_ulong = GET_RS2S (insn , regs );
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} else {
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regs -> epc = epc ;
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return -1 ;
@@ -539,7 +556,7 @@ static int handle_scalar_misaligned_store(struct pt_regs *regs)
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return - EOPNOTSUPP ;
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if (user_mode (regs )) {
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- if (copy_to_user ((u8 __user * )addr , & val , len ))
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+ if (copy_to_user_nofault ((u8 __user * )addr , & val , len ))
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return -1 ;
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} else {
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memcpy ((u8 * )addr , & val , len );
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