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cjubranSaeed Mahameed
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net/mlx5: Verify support for scheduling element and TSAR type
Before creating a scheduling element in a NIC or E-Switch scheduler, ensure that the requested element type is supported. If the element is of type Transmit Scheduling Arbiter (TSAR), also verify that the specific TSAR type is supported. Fixes: 214baf2 ("net/mlx5e: Support HTB offload") Fixes: 85c5f7c ("net/mlx5: E-switch, Create QoS on demand") Fixes: 0fe132e ("net/mlx5: E-switch, Allow to add vports to rate groups") Signed-off-by: Carolina Jubran <[email protected]> Reviewed-by: Cosmin Ratiu <[email protected]> Signed-off-by: Saeed Mahameed <[email protected]>
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2 files changed

+31
-20
lines changed
  • drivers/net/ethernet/mellanox/mlx5/core

2 files changed

+31
-20
lines changed

drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c

Lines changed: 24 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -312,6 +312,25 @@ static int esw_qos_set_group_max_rate(struct mlx5_eswitch *esw,
312312
return err;
313313
}
314314

315+
static bool esw_qos_element_type_supported(struct mlx5_core_dev *dev, int type)
316+
{
317+
switch (type) {
318+
case SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR:
319+
return MLX5_CAP_QOS(dev, esw_element_type) &
320+
ELEMENT_TYPE_CAP_MASK_TSAR;
321+
case SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT:
322+
return MLX5_CAP_QOS(dev, esw_element_type) &
323+
ELEMENT_TYPE_CAP_MASK_VPORT;
324+
case SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC:
325+
return MLX5_CAP_QOS(dev, esw_element_type) &
326+
ELEMENT_TYPE_CAP_MASK_VPORT_TC;
327+
case SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC:
328+
return MLX5_CAP_QOS(dev, esw_element_type) &
329+
ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC;
330+
}
331+
return false;
332+
}
333+
315334
static int esw_qos_vport_create_sched_element(struct mlx5_eswitch *esw,
316335
struct mlx5_vport *vport,
317336
u32 max_rate, u32 bw_share)
@@ -323,6 +342,9 @@ static int esw_qos_vport_create_sched_element(struct mlx5_eswitch *esw,
323342
void *vport_elem;
324343
int err;
325344

345+
if (!esw_qos_element_type_supported(dev, SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT))
346+
return -EOPNOTSUPP;
347+
326348
parent_tsar_ix = group ? group->tsar_ix : esw->qos.root_tsar_ix;
327349
MLX5_SET(scheduling_context, sched_ctx, element_type,
328350
SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT);
@@ -533,25 +555,6 @@ static int esw_qos_destroy_rate_group(struct mlx5_eswitch *esw,
533555
return err;
534556
}
535557

536-
static bool esw_qos_element_type_supported(struct mlx5_core_dev *dev, int type)
537-
{
538-
switch (type) {
539-
case SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR:
540-
return MLX5_CAP_QOS(dev, esw_element_type) &
541-
ELEMENT_TYPE_CAP_MASK_TSAR;
542-
case SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT:
543-
return MLX5_CAP_QOS(dev, esw_element_type) &
544-
ELEMENT_TYPE_CAP_MASK_VPORT;
545-
case SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC:
546-
return MLX5_CAP_QOS(dev, esw_element_type) &
547-
ELEMENT_TYPE_CAP_MASK_VPORT_TC;
548-
case SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC:
549-
return MLX5_CAP_QOS(dev, esw_element_type) &
550-
ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC;
551-
}
552-
return false;
553-
}
554-
555558
static int esw_qos_create(struct mlx5_eswitch *esw, struct netlink_ext_ack *extack)
556559
{
557560
u32 tsar_ctx[MLX5_ST_SZ_DW(scheduling_context)] = {};
@@ -562,7 +565,8 @@ static int esw_qos_create(struct mlx5_eswitch *esw, struct netlink_ext_ack *exta
562565
if (!MLX5_CAP_GEN(dev, qos) || !MLX5_CAP_QOS(dev, esw_scheduling))
563566
return -EOPNOTSUPP;
564567

565-
if (!esw_qos_element_type_supported(dev, SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR))
568+
if (!esw_qos_element_type_supported(dev, SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR) ||
569+
!(MLX5_CAP_QOS(dev, esw_tsar_type) & TSAR_TYPE_CAP_MASK_DWRR))
566570
return -EOPNOTSUPP;
567571

568572
MLX5_SET(scheduling_context, tsar_ctx, element_type,

drivers/net/ethernet/mellanox/mlx5/core/qos.c

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -28,6 +28,9 @@ int mlx5_qos_create_leaf_node(struct mlx5_core_dev *mdev, u32 parent_id,
2828
{
2929
u32 sched_ctx[MLX5_ST_SZ_DW(scheduling_context)] = {0};
3030

31+
if (!(MLX5_CAP_QOS(mdev, nic_element_type) & ELEMENT_TYPE_CAP_MASK_QUEUE_GROUP))
32+
return -EOPNOTSUPP;
33+
3134
MLX5_SET(scheduling_context, sched_ctx, parent_element_id, parent_id);
3235
MLX5_SET(scheduling_context, sched_ctx, element_type,
3336
SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP);
@@ -44,6 +47,10 @@ int mlx5_qos_create_inner_node(struct mlx5_core_dev *mdev, u32 parent_id,
4447
u32 sched_ctx[MLX5_ST_SZ_DW(scheduling_context)] = {0};
4548
void *attr;
4649

50+
if (!(MLX5_CAP_QOS(mdev, nic_element_type) & ELEMENT_TYPE_CAP_MASK_TSAR) ||
51+
!(MLX5_CAP_QOS(mdev, nic_tsar_type) & TSAR_TYPE_CAP_MASK_DWRR))
52+
return -EOPNOTSUPP;
53+
4754
MLX5_SET(scheduling_context, sched_ctx, parent_element_id, parent_id);
4855
MLX5_SET(scheduling_context, sched_ctx, element_type,
4956
SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR);

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