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18 | 18 | #define OA_TC6_REG_STATUS0 0x0008
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19 | 19 | #define STATUS0_RESETC BIT(6) /* Reset Complete */
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20 | 20 |
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| 21 | +/* Interrupt Mask Register #0 */ |
| 22 | +#define OA_TC6_REG_INT_MASK0 0x000C |
| 23 | +#define INT_MASK0_HEADER_ERR_MASK BIT(5) |
| 24 | +#define INT_MASK0_LOSS_OF_FRAME_ERR_MASK BIT(4) |
| 25 | +#define INT_MASK0_RX_BUFFER_OVERFLOW_ERR_MASK BIT(3) |
| 26 | +#define INT_MASK0_TX_PROTOCOL_ERR_MASK BIT(0) |
| 27 | + |
21 | 28 | /* Control command header */
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22 | 29 | #define OA_TC6_CTRL_HEADER_DATA_NOT_CTRL BIT(31)
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23 | 30 | #define OA_TC6_CTRL_HEADER_WRITE_NOT_READ BIT(29)
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@@ -327,6 +334,23 @@ static int oa_tc6_sw_reset_macphy(struct oa_tc6 *tc6)
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327 | 334 | return oa_tc6_write_register(tc6, OA_TC6_REG_STATUS0, regval);
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328 | 335 | }
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329 | 336 |
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| 337 | +static int oa_tc6_unmask_macphy_error_interrupts(struct oa_tc6 *tc6) |
| 338 | +{ |
| 339 | + u32 regval; |
| 340 | + int ret; |
| 341 | + |
| 342 | + ret = oa_tc6_read_register(tc6, OA_TC6_REG_INT_MASK0, ®val); |
| 343 | + if (ret) |
| 344 | + return ret; |
| 345 | + |
| 346 | + regval &= ~(INT_MASK0_TX_PROTOCOL_ERR_MASK | |
| 347 | + INT_MASK0_RX_BUFFER_OVERFLOW_ERR_MASK | |
| 348 | + INT_MASK0_LOSS_OF_FRAME_ERR_MASK | |
| 349 | + INT_MASK0_HEADER_ERR_MASK); |
| 350 | + |
| 351 | + return oa_tc6_write_register(tc6, OA_TC6_REG_INT_MASK0, regval); |
| 352 | +} |
| 353 | + |
330 | 354 | /**
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331 | 355 | * oa_tc6_init - allocates and initializes oa_tc6 structure.
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332 | 356 | * @spi: device with which data will be exchanged.
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@@ -369,6 +393,13 @@ struct oa_tc6 *oa_tc6_init(struct spi_device *spi)
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369 | 393 | return NULL;
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370 | 394 | }
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371 | 395 |
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| 396 | + ret = oa_tc6_unmask_macphy_error_interrupts(tc6); |
| 397 | + if (ret) { |
| 398 | + dev_err(&tc6->spi->dev, |
| 399 | + "MAC-PHY error interrupts unmask failed: %d\n", ret); |
| 400 | + return NULL; |
| 401 | + } |
| 402 | + |
372 | 403 | return tc6;
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373 | 404 | }
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374 | 405 | EXPORT_SYMBOL_GPL(oa_tc6_init);
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