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Merge tag 'irq-urgent-2023-10-10-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull irq fixes from Thomas Gleixner: "A set of updates for interrupt chip drivers: - Fix the fail of the Qualcomm PDC driver on v3.2 hardware which is caused by a control bit being moved to a different location - Update the SM8150 device tree PDC resource so the version register can be read - Make the Renesas RZG2L driver correct for interrupts which are outside of the LSB in the TSSR register by using the proper macro for calculating the mask - Document the Renesas RZ2GL device tree binding correctly and update them for a few devices which faul to boot otherwise - Use the proper accessor in the RZ2GL driver instead of blindly dereferencing an unchecked pointer - Make GICv3 handle the dma-non-coherent attribute correctly - Ensure that all interrupt controller nodes on RISCV are marked as initialized correctly Maintainer changes: - Add a new entry for GIC interrupt controllers and assign Marc Zyngier as the maintainer - Remove Marc Zyngier from the core and driver maintainer entries as he is burried in work and short of time to handle that. Thanks to Marc for all the great work he has done in the past couple of years! Also note that commit 5873d38 ("irqchip/qcom-pdc: Add support for v3.2 HW") has a incorrect SOB chain. The real author is Neil. His patch was posted by Dmitry once and Neil picked it up from the list and reposted it with the bogus SOB chain. Not a big deal, but worth to mention. I wanted to fix that up, but then got distracted and Marc piled more changes on top. So I decided to leave it as is instead of rebasing world" * tag 'irq-urgent-2023-10-10-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: MAINTAINERS: Remove myself from the general IRQ subsystem maintenance MAINTAINERS: Add myself as the ARM GIC maintainer irqchip/renesas-rzg2l: Convert to irq_data_get_irq_chip_data() irqchip/stm32-exti: add missing DT IRQ flag translation irqchip/riscv-intc: Mark all INTC nodes as initialized irqchip/gic-v3: Enable non-coherent redistributors/ITSes DT probing irqchip/gic-v3-its: Split allocation from initialisation of its_node dt-bindings: interrupt-controller: arm,gic-v3: Add dma-noncoherent property dt-bindings: interrupt-controller: renesas,irqc: Add r8a779f0 support dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/G2UL SoC irqchip: renesas-rzg2l: Fix logic to clear TINT interrupt source dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Update description for '#interrupt-cells' property arm64: dts: qcom: sm8150: extend the size of the PDC resource irqchip/qcom-pdc: Add support for v3.2 HW
2 parents b711538 + 4dc5af1 commit 87813e1

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‎Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml

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@@ -106,6 +106,12 @@ properties:
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$ref: /schemas/types.yaml#/definitions/uint32
107107
maximum: 4096
108108

109+
dma-noncoherent:
110+
description:
111+
Present if the GIC redistributors permit programming shareability
112+
and cacheability attributes but are connected to a non-coherent
113+
downstream interconnect.
114+
109115
msi-controller:
110116
description:
111117
Only present if the Message Based Interrupt functionality is
@@ -193,6 +199,12 @@ patternProperties:
193199
compatible:
194200
const: arm,gic-v3-its
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202+
dma-noncoherent:
203+
description:
204+
Present if the GIC ITS permits programming shareability and
205+
cacheability attributes but is connected to a non-coherent
206+
downstream interconnect.
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msi-controller: true
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"#msi-cells":

‎Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.yaml

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@@ -37,6 +37,7 @@ properties:
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- renesas,intc-ex-r8a77990 # R-Car E3
3838
- renesas,intc-ex-r8a77995 # R-Car D3
3939
- renesas,intc-ex-r8a779a0 # R-Car V3U
40+
- renesas,intc-ex-r8a779f0 # R-Car S4-8
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- renesas,intc-ex-r8a779g0 # R-Car V4H
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- const: renesas,irqc
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‎Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml

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Original file line numberDiff line numberDiff line change
@@ -19,20 +19,19 @@ description: |
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- NMI edge select (NMI is not treated as NMI exception and supports fall edge and
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stand-up edge detection interrupts)
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allOf:
23-
- $ref: /schemas/interrupt-controller.yaml#
24-
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properties:
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compatible:
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items:
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- enum:
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- renesas,r9a07g043u-irqc # RZ/G2UL
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- renesas,r9a07g044-irqc # RZ/G2{L,LC}
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- renesas,r9a07g054-irqc # RZ/V2L
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- const: renesas,rzg2l-irqc
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3331
'#interrupt-cells':
34-
description: The first cell should contain external interrupt number (IRQ0-7) and the
35-
second cell is used to specify the flag.
32+
description: The first cell should contain a macro RZG2L_{NMI,IRQX} included in the
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include/dt-bindings/interrupt-controller/irqc-rzg2l.h and the second
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cell is used to specify the flag.
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const: 2
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'#address-cells':
@@ -44,7 +43,96 @@ properties:
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maxItems: 1
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4645
interrupts:
47-
maxItems: 41
46+
minItems: 41
47+
items:
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- description: NMI interrupt
49+
- description: IRQ0 interrupt
50+
- description: IRQ1 interrupt
51+
- description: IRQ2 interrupt
52+
- description: IRQ3 interrupt
53+
- description: IRQ4 interrupt
54+
- description: IRQ5 interrupt
55+
- description: IRQ6 interrupt
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- description: IRQ7 interrupt
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- description: GPIO interrupt, TINT0
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- description: GPIO interrupt, TINT1
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- description: GPIO interrupt, TINT2
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- description: GPIO interrupt, TINT3
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- description: GPIO interrupt, TINT4
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- description: GPIO interrupt, TINT5
63+
- description: GPIO interrupt, TINT6
64+
- description: GPIO interrupt, TINT7
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- description: GPIO interrupt, TINT8
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- description: GPIO interrupt, TINT9
67+
- description: GPIO interrupt, TINT10
68+
- description: GPIO interrupt, TINT11
69+
- description: GPIO interrupt, TINT12
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- description: GPIO interrupt, TINT13
71+
- description: GPIO interrupt, TINT14
72+
- description: GPIO interrupt, TINT15
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- description: GPIO interrupt, TINT16
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- description: GPIO interrupt, TINT17
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- description: GPIO interrupt, TINT18
76+
- description: GPIO interrupt, TINT19
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- description: GPIO interrupt, TINT20
78+
- description: GPIO interrupt, TINT21
79+
- description: GPIO interrupt, TINT22
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- description: GPIO interrupt, TINT23
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- description: GPIO interrupt, TINT24
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- description: GPIO interrupt, TINT25
83+
- description: GPIO interrupt, TINT26
84+
- description: GPIO interrupt, TINT27
85+
- description: GPIO interrupt, TINT28
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- description: GPIO interrupt, TINT29
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- description: GPIO interrupt, TINT30
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- description: GPIO interrupt, TINT31
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- description: Bus error interrupt
90+
91+
interrupt-names:
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minItems: 41
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items:
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- const: nmi
95+
- const: irq0
96+
- const: irq1
97+
- const: irq2
98+
- const: irq3
99+
- const: irq4
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- const: irq5
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- const: irq6
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- const: irq7
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- const: tint0
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- const: tint1
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- const: tint2
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- const: tint3
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- const: tint4
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- const: tint5
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- const: tint6
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- const: tint7
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- const: tint8
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- const: tint9
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- const: tint10
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- const: tint11
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- const: tint12
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- const: tint13
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- const: tint14
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- const: tint15
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- const: tint16
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- const: tint17
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- const: tint18
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- const: tint19
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- const: tint20
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- const: tint21
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- const: tint22
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- const: tint23
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- const: tint24
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- const: tint25
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- const: tint26
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- const: tint27
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- const: tint28
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- const: tint29
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- const: tint30
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- const: tint31
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- const: bus-err
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clocks:
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maxItems: 2
@@ -72,6 +160,23 @@ required:
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- power-domains
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- resets
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allOf:
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- $ref: /schemas/interrupt-controller.yaml#
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- if:
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properties:
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compatible:
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contains:
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const: renesas,r9a07g043u-irqc
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then:
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properties:
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interrupts:
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minItems: 42
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interrupt-names:
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minItems: 42
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required:
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- interrupt-names
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unevaluatedProperties: false
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examples:
@@ -80,55 +185,66 @@ examples:
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#include <dt-bindings/clock/r9a07g044-cpg.h>
81186
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irqc: interrupt-controller@110a0000 {
83-
compatible = "renesas,r9a07g044-irqc", "renesas,rzg2l-irqc";
84-
reg = <0x110a0000 0x10000>;
85-
#interrupt-cells = <2>;
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#address-cells = <0>;
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interrupt-controller;
88-
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
89-
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
90-
<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
91-
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
92-
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
93-
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
94-
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
95-
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
96-
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
97-
<GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
98-
<GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>,
99-
<GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
100-
<GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
101-
<GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
104-
<GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
105-
<GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
106-
<GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>,
107-
<GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>,
108-
<GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
109-
<GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
112-
<GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
113-
<GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
114-
<GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,
115-
<GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
116-
<GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
117-
<GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
118-
<GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
119-
<GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
120-
<GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
121-
<GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
122-
<GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
123-
<GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
124-
<GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
125-
<GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
126-
<GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
127-
<GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
128-
<GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>;
129-
clocks = <&cpg CPG_MOD R9A07G044_IA55_CLK>,
130-
<&cpg CPG_MOD R9A07G044_IA55_PCLK>;
131-
clock-names = "clk", "pclk";
132-
power-domains = <&cpg>;
133-
resets = <&cpg R9A07G044_IA55_RESETN>;
188+
compatible = "renesas,r9a07g044-irqc", "renesas,rzg2l-irqc";
189+
reg = <0x110a0000 0x10000>;
190+
#interrupt-cells = <2>;
191+
#address-cells = <0>;
192+
interrupt-controller;
193+
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
194+
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
195+
<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
196+
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
197+
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
198+
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
202+
<GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>,
212+
<GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
214+
<GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
216+
<GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
218+
<GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
219+
<GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,
220+
<GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
224+
<GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
225+
<GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
226+
<GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
227+
<GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
228+
<GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
229+
<GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
230+
<GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
231+
<GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
232+
<GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
233+
<GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>;
234+
interrupt-names = "nmi",
235+
"irq0", "irq1", "irq2", "irq3",
236+
"irq4", "irq5", "irq6", "irq7",
237+
"tint0", "tint1", "tint2", "tint3",
238+
"tint4", "tint5", "tint6", "tint7",
239+
"tint8", "tint9", "tint10", "tint11",
240+
"tint12", "tint13", "tint14", "tint15",
241+
"tint16", "tint17", "tint18", "tint19",
242+
"tint20", "tint21", "tint22", "tint23",
243+
"tint24", "tint25", "tint26", "tint27",
244+
"tint28", "tint29", "tint30", "tint31";
245+
clocks = <&cpg CPG_MOD R9A07G044_IA55_CLK>,
246+
<&cpg CPG_MOD R9A07G044_IA55_PCLK>;
247+
clock-names = "clk", "pclk";
248+
power-domains = <&cpg>;
249+
resets = <&cpg R9A07G044_IA55_RESETN>;
134250
};

‎MAINTAINERS

Lines changed: 12 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1584,6 +1584,17 @@ F: arch/arm/include/asm/arch_timer.h
15841584
F: arch/arm64/include/asm/arch_timer.h
15851585
F: drivers/clocksource/arm_arch_timer.c
15861586

1587+
ARM GENERIC INTERRUPT CONTROLLER DRIVERS
1588+
M: Marc Zyngier <[email protected]>
1589+
L: [email protected] (moderated for non-subscribers)
1590+
S: Maintained
1591+
F: Documentation/devicetree/bindings/interrupt-controller/arm,gic*
1592+
F: arch/arm/include/asm/arch_gicv3.h
1593+
F: arch/arm64/include/asm/arch_gicv3.h
1594+
F: drivers/irqchip/irq-gic*.[ch]
1595+
F: include/linux/irqchip/arm-gic*.h
1596+
F: include/linux/irqchip/arm-vgic-info.h
1597+
15871598
ARM HDLCD DRM DRIVER
15881599
M: Liviu Dudau <[email protected]>
15891600
S: Supported
@@ -11060,7 +11071,7 @@ F: Documentation/devicetree/bindings/sound/irondevice,*
1106011071
F: sound/soc/codecs/sma*
1106111072

1106211073
IRQ DOMAINS (IRQ NUMBER MAPPING LIBRARY)
11063-
M: Marc Zyngier <[email protected]>
11074+
M: Thomas Gleixner <[email protected]>
1106411075
S: Maintained
1106511076
T: git git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git irq/core
1106611077
F: Documentation/core-api/irq/irq-domain.rst
@@ -11079,7 +11090,6 @@ F: lib/group_cpus.c
1107911090

1108011091
IRQCHIP DRIVERS
1108111092
M: Thomas Gleixner <[email protected]>
11082-
M: Marc Zyngier <[email protected]>
1108311093
L: [email protected]
1108411094
S: Maintained
1108511095
T: git git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git irq/core

‎arch/arm64/boot/dts/qcom/sm8150.dtsi

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3958,7 +3958,7 @@
39583958

39593959
pdc: interrupt-controller@b220000 {
39603960
compatible = "qcom,sm8150-pdc", "qcom,pdc";
3961-
reg = <0 0x0b220000 0 0x400>;
3961+
reg = <0 0x0b220000 0 0x30000>;
39623962
qcom,pdc-ranges = <0 480 94>, <94 609 31>,
39633963
<125 63 1>;
39643964
#interrupt-cells = <2>;

‎drivers/irqchip/irq-gic-common.h

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -29,4 +29,8 @@ void gic_enable_quirks(u32 iidr, const struct gic_quirk *quirks,
2929
void gic_enable_of_quirks(const struct device_node *np,
3030
const struct gic_quirk *quirks, void *data);
3131

32+
#define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING (1 << 0)
33+
#define RDIST_FLAGS_RD_TABLES_PREALLOCATED (1 << 1)
34+
#define RDIST_FLAGS_FORCE_NON_SHAREABLE (1 << 2)
35+
3236
#endif /* _IRQ_GIC_COMMON_H */

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