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547 | 547 | #define IMX_SC_R_ATTESTATION 545
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548 | 548 | #define IMX_SC_R_LAST 546
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549 | 549 |
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| 550 | +/* |
| 551 | + * Defines for SC PM CLK |
| 552 | + */ |
| 553 | +#define IMX_SC_PM_CLK_SLV_BUS 0 /* Slave bus clock */ |
| 554 | +#define IMX_SC_PM_CLK_MST_BUS 1 /* Master bus clock */ |
| 555 | +#define IMX_SC_PM_CLK_PER 2 /* Peripheral clock */ |
| 556 | +#define IMX_SC_PM_CLK_PHY 3 /* Phy clock */ |
| 557 | +#define IMX_SC_PM_CLK_MISC 4 /* Misc clock */ |
| 558 | +#define IMX_SC_PM_CLK_MISC0 0 /* Misc 0 clock */ |
| 559 | +#define IMX_SC_PM_CLK_MISC1 1 /* Misc 1 clock */ |
| 560 | +#define IMX_SC_PM_CLK_MISC2 2 /* Misc 2 clock */ |
| 561 | +#define IMX_SC_PM_CLK_MISC3 3 /* Misc 3 clock */ |
| 562 | +#define IMX_SC_PM_CLK_MISC4 4 /* Misc 4 clock */ |
| 563 | +#define IMX_SC_PM_CLK_CPU 2 /* CPU clock */ |
| 564 | +#define IMX_SC_PM_CLK_PLL 4 /* PLL */ |
| 565 | +#define IMX_SC_PM_CLK_BYPASS 4 /* Bypass clock */ |
| 566 | + |
550 | 567 | /*
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551 | 568 | * Defines for SC CONTROL
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552 | 569 | */
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596 | 613 | #define IMX_SC_C_RST0 43
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597 | 614 | #define IMX_SC_C_RST1 44
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598 | 615 | #define IMX_SC_C_SEL0 45
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599 |
| -#define IMX_SC_C_LAST 46 |
| 616 | +#define IMX_SC_C_CALIB0 46 |
| 617 | +#define IMX_SC_C_CALIB1 47 |
| 618 | +#define IMX_SC_C_CALIB2 48 |
| 619 | +#define IMX_SC_C_IPG_DEBUG 49 |
| 620 | +#define IMX_SC_C_IPG_DOZE 50 |
| 621 | +#define IMX_SC_C_IPG_WAIT 51 |
| 622 | +#define IMX_SC_C_IPG_STOP 52 |
| 623 | +#define IMX_SC_C_IPG_STOP_MODE 53 |
| 624 | +#define IMX_SC_C_IPG_STOP_ACK 54 |
| 625 | +#define IMX_SC_C_SYNC_CTRL 55 |
| 626 | +#define IMX_SC_C_OFS_AUDIO_ALT 56 |
| 627 | +#define IMX_SC_C_DSP_BYP 57 |
| 628 | +#define IMX_SC_C_CLK_GEN_EN 58 |
| 629 | +#define IMX_SC_C_INTF_SEL 59 |
| 630 | +#define IMX_SC_C_RXC_DLY 60 |
| 631 | +#define IMX_SC_C_TIMER_SEL 61 |
| 632 | +#define IMX_SC_C_LAST 62 |
600 | 633 |
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601 | 634 | #endif /* __DT_BINDINGS_RSCRC_IMX_H */
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