|
50 | 50 | no-map;
|
51 | 51 | };
|
52 | 52 |
|
| 53 | + wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { |
| 54 | + compatible = "shared-dma-pool"; |
| 55 | + reg = <0x00 0xa0000000 0x00 0x100000>; |
| 56 | + no-map; |
| 57 | + }; |
| 58 | + |
53 | 59 | wkup_r5fss0_core0_memory_region: r5f-memory@a0100000 {
|
54 | 60 | compatible = "shared-dma-pool";
|
55 | 61 | reg = <0x00 0xa0100000 0x00 0xf00000>;
|
56 | 62 | no-map;
|
57 | 63 | };
|
| 64 | + |
| 65 | + mcu_r5fss0_core0_dma_memory_region: mcu-r5fss-dma-memory-region@a1000000 { |
| 66 | + compatible = "shared-dma-pool"; |
| 67 | + reg = <0x00 0xa1000000 0x00 0x100000>; |
| 68 | + no-map; |
| 69 | + }; |
| 70 | + |
| 71 | + mcu_r5fss0_core0_memory_region: mcu-r5fss-memory-region@a1100000 { |
| 72 | + compatible = "shared-dma-pool"; |
| 73 | + reg = <0x00 0xa1100000 0x00 0xf00000>; |
| 74 | + no-map; |
| 75 | + }; |
| 76 | + |
| 77 | + main_r5fss0_core0_dma_memory_region: main-r5fss-dma-memory-region@a2000000 { |
| 78 | + compatible = "shared-dma-pool"; |
| 79 | + reg = <0x00 0xa2000000 0x00 0x100000>; |
| 80 | + no-map; |
| 81 | + }; |
| 82 | + |
| 83 | + main_r5fss0_core0_memory_region: main-r5fss-memory-region@a2100000 { |
| 84 | + compatible = "shared-dma-pool"; |
| 85 | + reg = <0x00 0xa2100000 0x00 0xf00000>; |
| 86 | + no-map; |
| 87 | + }; |
| 88 | + |
| 89 | + c7x_0_dma_memory_region: c7x-dma-memory@a3000000 { |
| 90 | + compatible = "shared-dma-pool"; |
| 91 | + reg = <0x00 0xa3000000 0x00 0x100000>; |
| 92 | + no-map; |
| 93 | + }; |
| 94 | + |
| 95 | + c7x_0_memory_region: c7x-memory@a3100000 { |
| 96 | + compatible = "shared-dma-pool"; |
| 97 | + reg = <0x00 0xa3100000 0x00 0xf00000>; |
| 98 | + no-map; |
| 99 | + }; |
| 100 | + |
| 101 | + c7x_1_dma_memory_region: c7x-dma-memory@a4000000 { |
| 102 | + compatible = "shared-dma-pool"; |
| 103 | + reg = <0x00 0xa4000000 0x00 0x100000>; |
| 104 | + no-map; |
| 105 | + }; |
| 106 | + |
| 107 | + c7x_1_memory_region: c7x-memory@a4100000 { |
| 108 | + compatible = "shared-dma-pool"; |
| 109 | + reg = <0x00 0xa4100000 0x00 0xf00000>; |
| 110 | + no-map; |
| 111 | + }; |
| 112 | + |
| 113 | + rtos_ipc_memory_region: ipc-memories@a5000000 { |
| 114 | + reg = <0x00 0xa5000000 0x00 0x1c00000>; |
| 115 | + alignment = <0x1000>; |
| 116 | + no-map; |
| 117 | + }; |
58 | 118 | };
|
59 | 119 |
|
60 | 120 | vsys_5v0: regulator-1 {
|
|
391 | 451 | ti,fails-without-test-cd;
|
392 | 452 | status = "okay";
|
393 | 453 | };
|
| 454 | + |
| 455 | +&mailbox0_cluster0 { |
| 456 | + status = "okay"; |
| 457 | + |
| 458 | + mbox_wkup_r5_0: mbox-wkup-r5-0 { |
| 459 | + ti,mbox-rx = <0 0 0>; |
| 460 | + ti,mbox-tx = <1 0 0>; |
| 461 | + }; |
| 462 | +}; |
| 463 | + |
| 464 | +&mailbox0_cluster1 { |
| 465 | + status = "okay"; |
| 466 | + |
| 467 | + mbox_mcu_r5_0: mbox-mcu-r5-0 { |
| 468 | + ti,mbox-rx = <0 0 0>; |
| 469 | + ti,mbox-tx = <1 0 0>; |
| 470 | + }; |
| 471 | +}; |
| 472 | + |
| 473 | +&mailbox0_cluster2 { |
| 474 | + status = "okay"; |
| 475 | + |
| 476 | + mbox_c7x_0: mbox-c7x-0 { |
| 477 | + ti,mbox-rx = <0 0 0>; |
| 478 | + ti,mbox-tx = <1 0 0>; |
| 479 | + }; |
| 480 | +}; |
| 481 | + |
| 482 | +&mailbox0_cluster3 { |
| 483 | + status = "okay"; |
| 484 | + |
| 485 | + mbox_main_r5_0: mbox-main-r5-0 { |
| 486 | + ti,mbox-rx = <0 0 0>; |
| 487 | + ti,mbox-tx = <1 0 0>; |
| 488 | + }; |
| 489 | + |
| 490 | + mbox_c7x_1: mbox-c7x-1 { |
| 491 | + ti,mbox-rx = <2 0 0>; |
| 492 | + ti,mbox-tx = <3 0 0>; |
| 493 | + }; |
| 494 | +}; |
| 495 | + |
| 496 | +/* Timers are used by Remoteproc firmware */ |
| 497 | +&main_timer0 { |
| 498 | + status = "reserved"; |
| 499 | +}; |
| 500 | + |
| 501 | +&main_timer1 { |
| 502 | + status = "reserved"; |
| 503 | +}; |
| 504 | + |
| 505 | +&main_timer2 { |
| 506 | + status = "reserved"; |
| 507 | +}; |
| 508 | + |
| 509 | +&wkup_r5fss0 { |
| 510 | + status = "okay"; |
| 511 | +}; |
| 512 | + |
| 513 | +&wkup_r5fss0_core0 { |
| 514 | + mboxes = <&mailbox0_cluster0 &mbox_wkup_r5_0>; |
| 515 | + memory-region = <&wkup_r5fss0_core0_dma_memory_region>, |
| 516 | + <&wkup_r5fss0_core0_memory_region>; |
| 517 | +}; |
| 518 | + |
| 519 | +&mcu_r5fss0 { |
| 520 | + status = "okay"; |
| 521 | +}; |
| 522 | + |
| 523 | +&mcu_r5fss0_core0 { |
| 524 | + mboxes = <&mailbox0_cluster1 &mbox_mcu_r5_0>; |
| 525 | + memory-region = <&mcu_r5fss0_core0_dma_memory_region>, |
| 526 | + <&mcu_r5fss0_core0_memory_region>; |
| 527 | +}; |
| 528 | + |
| 529 | +&main_r5fss0 { |
| 530 | + status = "okay"; |
| 531 | +}; |
| 532 | + |
| 533 | +&main_r5fss0_core0 { |
| 534 | + mboxes = <&mailbox0_cluster3 &mbox_main_r5_0>; |
| 535 | + memory-region = <&main_r5fss0_core0_dma_memory_region>, |
| 536 | + <&main_r5fss0_core0_memory_region>; |
| 537 | +}; |
| 538 | + |
| 539 | +&c7x_0 { |
| 540 | + mboxes = <&mailbox0_cluster2 &mbox_c7x_0>; |
| 541 | + memory-region = <&c7x_0_dma_memory_region>, |
| 542 | + <&c7x_0_memory_region>; |
| 543 | + status = "okay"; |
| 544 | +}; |
| 545 | + |
| 546 | +&c7x_1 { |
| 547 | + mboxes = <&mailbox0_cluster3 &mbox_c7x_1>; |
| 548 | + memory-region = <&c7x_1_dma_memory_region>, |
| 549 | + <&c7x_1_memory_region>; |
| 550 | + status = "okay"; |
| 551 | +}; |
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