Skip to content

Commit 8a37cd4

Browse files
jnikulajnikula
committed
drm/i915/pps: convert intel_pps.[ch] to struct intel_display
Going forward, struct intel_display shall replace struct drm_i915_private as the main display device data pointer type. Convert intel_pps.[ch] to struct intel_display. Some stragglers are left behind where needed. Reviewed-by: Ville Syrjälä <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/bea51b0d9e4546ba21d0d4eb01ca1097fda095ab.1725012870.git.jani.nikula@intel.com
1 parent 631ef2e commit 8a37cd4

File tree

9 files changed

+299
-253
lines changed

9 files changed

+299
-253
lines changed

‎drivers/gpu/drm/i915/display/intel_display.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -7793,7 +7793,7 @@ void intel_setup_outputs(struct drm_i915_private *dev_priv)
77937793
struct intel_encoder *encoder;
77947794
bool dpd_is_edp = false;
77957795

7796-
intel_pps_unlock_regs_wa(dev_priv);
7796+
intel_pps_unlock_regs_wa(display);
77977797

77987798
if (!HAS_DISPLAY(dev_priv))
77997799
return;

‎drivers/gpu/drm/i915/display/intel_display_driver.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -428,7 +428,7 @@ int intel_display_driver_probe_nogem(struct drm_i915_private *i915)
428428

429429
intel_panel_sanitize_ssc(i915);
430430

431-
intel_pps_setup(i915);
431+
intel_pps_setup(display);
432432

433433
intel_gmbus_setup(i915);
434434

‎drivers/gpu/drm/i915/display/intel_display_power_well.c

Lines changed: 11 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -861,6 +861,8 @@ void skl_enable_dc6(struct drm_i915_private *dev_priv)
861861

862862
void bxt_enable_dc9(struct drm_i915_private *dev_priv)
863863
{
864+
struct intel_display *display = &dev_priv->display;
865+
864866
assert_can_enable_dc9(dev_priv);
865867

866868
drm_dbg_kms(&dev_priv->drm, "Enabling DC9\n");
@@ -870,19 +872,21 @@ void bxt_enable_dc9(struct drm_i915_private *dev_priv)
870872
* because PPS registers are always on.
871873
*/
872874
if (!HAS_PCH_SPLIT(dev_priv))
873-
intel_pps_reset_all(dev_priv);
875+
intel_pps_reset_all(display);
874876
gen9_set_dc_state(dev_priv, DC_STATE_EN_DC9);
875877
}
876878

877879
void bxt_disable_dc9(struct drm_i915_private *dev_priv)
878880
{
881+
struct intel_display *display = &dev_priv->display;
882+
879883
assert_can_disable_dc9(dev_priv);
880884

881885
drm_dbg_kms(&dev_priv->drm, "Disabling DC9\n");
882886

883887
gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
884888

885-
intel_pps_unlock_regs_wa(dev_priv);
889+
intel_pps_unlock_regs_wa(display);
886890
}
887891

888892
static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
@@ -1184,6 +1188,7 @@ static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
11841188

11851189
static void vlv_display_power_well_init(struct drm_i915_private *dev_priv)
11861190
{
1191+
struct intel_display *display = &dev_priv->display;
11871192
struct intel_encoder *encoder;
11881193
enum pipe pipe;
11891194

@@ -1229,19 +1234,21 @@ static void vlv_display_power_well_init(struct drm_i915_private *dev_priv)
12291234

12301235
intel_vga_redisable_power_on(dev_priv);
12311236

1232-
intel_pps_unlock_regs_wa(dev_priv);
1237+
intel_pps_unlock_regs_wa(display);
12331238
}
12341239

12351240
static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv)
12361241
{
1242+
struct intel_display *display = &dev_priv->display;
1243+
12371244
spin_lock_irq(&dev_priv->irq_lock);
12381245
valleyview_disable_display_irqs(dev_priv);
12391246
spin_unlock_irq(&dev_priv->irq_lock);
12401247

12411248
/* make sure we're done processing display irqs */
12421249
intel_synchronize_irq(dev_priv);
12431250

1244-
intel_pps_reset_all(dev_priv);
1251+
intel_pps_reset_all(display);
12451252

12461253
/* Prevent us from re-enabling polling on accident in late suspend */
12471254
if (!dev_priv->drm.dev->power.is_suspended)

‎drivers/gpu/drm/i915/display/intel_display_reset.c

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -83,7 +83,8 @@ void intel_display_reset_prepare(struct drm_i915_private *dev_priv)
8383

8484
void intel_display_reset_finish(struct drm_i915_private *i915)
8585
{
86-
struct drm_modeset_acquire_ctx *ctx = &i915->display.restore.reset_ctx;
86+
struct intel_display *display = &i915->display;
87+
struct drm_modeset_acquire_ctx *ctx = &display->restore.reset_ctx;
8788
struct drm_atomic_state *state;
8889
int ret;
8990

@@ -94,7 +95,7 @@ void intel_display_reset_finish(struct drm_i915_private *i915)
9495
if (!test_bit(I915_RESET_MODESET, &to_gt(i915)->reset.flags))
9596
return;
9697

97-
state = fetch_and_zero(&i915->display.restore.modeset_state);
98+
state = fetch_and_zero(&display->restore.modeset_state);
9899
if (!state)
99100
goto unlock;
100101

@@ -112,7 +113,7 @@ void intel_display_reset_finish(struct drm_i915_private *i915)
112113
* The display has been reset as well,
113114
* so need a full re-initialization.
114115
*/
115-
intel_pps_unlock_regs_wa(i915);
116+
intel_pps_unlock_regs_wa(display);
116117
intel_display_driver_init_hw(i915);
117118
intel_clock_gating_init(i915);
118119
intel_hpd_init(i915);

‎drivers/gpu/drm/i915/display/intel_dpll.c

Lines changed: 6 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1823,6 +1823,7 @@ static bool i9xx_has_pps(struct drm_i915_private *dev_priv)
18231823

18241824
void i9xx_enable_pll(const struct intel_crtc_state *crtc_state)
18251825
{
1826+
struct intel_display *display = to_intel_display(crtc_state);
18261827
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
18271828
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
18281829
const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
@@ -1833,7 +1834,7 @@ void i9xx_enable_pll(const struct intel_crtc_state *crtc_state)
18331834

18341835
/* PLL is protected by panel, make sure we can write it */
18351836
if (i9xx_has_pps(dev_priv))
1836-
assert_pps_unlocked(dev_priv, pipe);
1837+
assert_pps_unlocked(display, pipe);
18371838

18381839
intel_de_write(dev_priv, FP0(pipe), hw_state->fp0);
18391840
intel_de_write(dev_priv, FP1(pipe), hw_state->fp1);
@@ -2004,6 +2005,7 @@ static void _vlv_enable_pll(const struct intel_crtc_state *crtc_state)
20042005

20052006
void vlv_enable_pll(const struct intel_crtc_state *crtc_state)
20062007
{
2008+
struct intel_display *display = to_intel_display(crtc_state);
20072009
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
20082010
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
20092011
const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
@@ -2012,7 +2014,7 @@ void vlv_enable_pll(const struct intel_crtc_state *crtc_state)
20122014
assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder);
20132015

20142016
/* PLL is protected by panel, make sure we can write it */
2015-
assert_pps_unlocked(dev_priv, pipe);
2017+
assert_pps_unlocked(display, pipe);
20162018

20172019
/* Enable Refclk */
20182020
intel_de_write(dev_priv, DPLL(dev_priv, pipe),
@@ -2150,6 +2152,7 @@ static void _chv_enable_pll(const struct intel_crtc_state *crtc_state)
21502152

21512153
void chv_enable_pll(const struct intel_crtc_state *crtc_state)
21522154
{
2155+
struct intel_display *display = to_intel_display(crtc_state);
21532156
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
21542157
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
21552158
const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
@@ -2158,7 +2161,7 @@ void chv_enable_pll(const struct intel_crtc_state *crtc_state)
21582161
assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder);
21592162

21602163
/* PLL is protected by panel, make sure we can write it */
2161-
assert_pps_unlocked(dev_priv, pipe);
2164+
assert_pps_unlocked(display, pipe);
21622165

21632166
/* Enable Refclk and SSC */
21642167
intel_de_write(dev_priv, DPLL(dev_priv, pipe),

‎drivers/gpu/drm/i915/display/intel_pch_display.c

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -358,6 +358,7 @@ void ilk_pch_pre_enable(struct intel_atomic_state *state,
358358
void ilk_pch_enable(struct intel_atomic_state *state,
359359
struct intel_crtc *crtc)
360360
{
361+
struct intel_display *display = to_intel_display(state);
361362
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
362363
const struct intel_crtc_state *crtc_state =
363364
intel_atomic_get_new_crtc_state(state, crtc);
@@ -399,7 +400,7 @@ void ilk_pch_enable(struct intel_atomic_state *state,
399400
intel_enable_shared_dpll(crtc_state);
400401

401402
/* set transcoder timing, panel must allow it */
402-
assert_pps_unlocked(dev_priv, pipe);
403+
assert_pps_unlocked(display, pipe);
403404
if (intel_crtc_has_dp_encoder(crtc_state)) {
404405
intel_pch_transcoder_set_m1_n1(crtc, &crtc_state->dp_m_n);
405406
intel_pch_transcoder_set_m2_n2(crtc, &crtc_state->dp_m2_n2);

0 commit comments

Comments
 (0)