@@ -74,7 +74,6 @@ static void uv_rtc_send_IPI(int cpu)
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apicid = cpu_physical_id (cpu );
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pnode = uv_apicid_to_pnode (apicid );
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- apicid |= uv_apicid_hibits ;
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val = (1UL << UVH_IPI_INT_SEND_SHFT ) |
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(apicid << UVH_IPI_INT_APIC_ID_SHFT ) |
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(X86_PLATFORM_IPI_VECTOR << UVH_IPI_INT_VECTOR_SHFT );
@@ -85,10 +84,7 @@ static void uv_rtc_send_IPI(int cpu)
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/* Check for an RTC interrupt pending */
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static int uv_intr_pending (int pnode )
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{
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- if (is_uv1_hub ())
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- return uv_read_global_mmr64 (pnode , UVH_EVENT_OCCURRED0 ) &
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- UV1H_EVENT_OCCURRED0_RTC1_MASK ;
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- else if (is_uvx_hub ())
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+ if (is_uvx_hub ())
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return uv_read_global_mmr64 (pnode , UVXH_EVENT_OCCURRED2 ) &
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UVXH_EVENT_OCCURRED2_RTC_1_MASK ;
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return 0 ;
@@ -98,19 +94,15 @@ static int uv_intr_pending(int pnode)
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static int uv_setup_intr (int cpu , u64 expires )
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{
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u64 val ;
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- unsigned long apicid = cpu_physical_id (cpu ) | uv_apicid_hibits ;
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+ unsigned long apicid = cpu_physical_id (cpu );
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int pnode = uv_cpu_to_pnode (cpu );
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uv_write_global_mmr64 (pnode , UVH_RTC1_INT_CONFIG ,
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UVH_RTC1_INT_CONFIG_M_MASK );
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uv_write_global_mmr64 (pnode , UVH_INT_CMPB , -1L );
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- if (is_uv1_hub ())
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- uv_write_global_mmr64 (pnode , UVH_EVENT_OCCURRED0_ALIAS ,
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- UV1H_EVENT_OCCURRED0_RTC1_MASK );
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- else
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- uv_write_global_mmr64 (pnode , UVXH_EVENT_OCCURRED2_ALIAS ,
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- UVXH_EVENT_OCCURRED2_RTC_1_MASK );
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+ uv_write_global_mmr64 (pnode , UVXH_EVENT_OCCURRED2_ALIAS ,
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+ UVXH_EVENT_OCCURRED2_RTC_1_MASK );
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val = (X86_PLATFORM_IPI_VECTOR << UVH_RTC1_INT_CONFIG_VECTOR_SHFT ) |
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((u64 )apicid << UVH_RTC1_INT_CONFIG_APIC_ID_SHFT );
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