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x86/cpu/amd: Move the errata checking functionality up
Avoid new and remove old forward declarations. No functional changes. Signed-off-by: Borislav Petkov (AMD) <[email protected]>
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arch/x86/kernel/cpu/amd.c

Lines changed: 67 additions & 72 deletions
Original file line numberDiff line numberDiff line change
@@ -27,18 +27,80 @@
2727

2828
#include "cpu.h"
2929

30-
static const int amd_erratum_383[];
31-
static const int amd_erratum_400[];
32-
static const int amd_erratum_1054[];
33-
static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum);
34-
3530
/*
3631
* nodes_per_socket: Stores the number of nodes per socket.
3732
* Refer to Fam15h Models 00-0fh BKDG - CPUID Fn8000_001E_ECX
3833
* Node Identifiers[10:8]
3934
*/
4035
static u32 nodes_per_socket = 1;
4136

37+
/*
38+
* AMD errata checking
39+
*
40+
* Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or
41+
* AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that
42+
* have an OSVW id assigned, which it takes as first argument. Both take a
43+
* variable number of family-specific model-stepping ranges created by
44+
* AMD_MODEL_RANGE().
45+
*
46+
* Example:
47+
*
48+
* const int amd_erratum_319[] =
49+
* AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2),
50+
* AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0),
51+
* AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0));
52+
*/
53+
54+
#define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 }
55+
#define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 }
56+
#define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \
57+
((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end))
58+
#define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff)
59+
#define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff)
60+
#define AMD_MODEL_RANGE_END(range) ((range) & 0xfff)
61+
62+
static const int amd_erratum_400[] =
63+
AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf),
64+
AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf));
65+
66+
static const int amd_erratum_383[] =
67+
AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf));
68+
69+
/* #1054: Instructions Retired Performance Counter May Be Inaccurate */
70+
static const int amd_erratum_1054[] =
71+
AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0, 0, 0x2f, 0xf));
72+
73+
static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum)
74+
{
75+
int osvw_id = *erratum++;
76+
u32 range;
77+
u32 ms;
78+
79+
if (osvw_id >= 0 && osvw_id < 65536 &&
80+
cpu_has(cpu, X86_FEATURE_OSVW)) {
81+
u64 osvw_len;
82+
83+
rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len);
84+
if (osvw_id < osvw_len) {
85+
u64 osvw_bits;
86+
87+
rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6),
88+
osvw_bits);
89+
return osvw_bits & (1ULL << (osvw_id & 0x3f));
90+
}
91+
}
92+
93+
/* OSVW unavailable or ID unknown, match family-model-stepping range */
94+
ms = (cpu->x86_model << 4) | cpu->x86_stepping;
95+
while ((range = *erratum++))
96+
if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) &&
97+
(ms >= AMD_MODEL_RANGE_START(range)) &&
98+
(ms <= AMD_MODEL_RANGE_END(range)))
99+
return true;
100+
101+
return false;
102+
}
103+
42104
static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p)
43105
{
44106
u32 gprs[8] = { 0 };
@@ -1115,73 +1177,6 @@ static const struct cpu_dev amd_cpu_dev = {
11151177

11161178
cpu_dev_register(amd_cpu_dev);
11171179

1118-
/*
1119-
* AMD errata checking
1120-
*
1121-
* Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or
1122-
* AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that
1123-
* have an OSVW id assigned, which it takes as first argument. Both take a
1124-
* variable number of family-specific model-stepping ranges created by
1125-
* AMD_MODEL_RANGE().
1126-
*
1127-
* Example:
1128-
*
1129-
* const int amd_erratum_319[] =
1130-
* AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2),
1131-
* AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0),
1132-
* AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0));
1133-
*/
1134-
1135-
#define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 }
1136-
#define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 }
1137-
#define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \
1138-
((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end))
1139-
#define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff)
1140-
#define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff)
1141-
#define AMD_MODEL_RANGE_END(range) ((range) & 0xfff)
1142-
1143-
static const int amd_erratum_400[] =
1144-
AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf),
1145-
AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf));
1146-
1147-
static const int amd_erratum_383[] =
1148-
AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf));
1149-
1150-
/* #1054: Instructions Retired Performance Counter May Be Inaccurate */
1151-
static const int amd_erratum_1054[] =
1152-
AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0, 0, 0x2f, 0xf));
1153-
1154-
static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum)
1155-
{
1156-
int osvw_id = *erratum++;
1157-
u32 range;
1158-
u32 ms;
1159-
1160-
if (osvw_id >= 0 && osvw_id < 65536 &&
1161-
cpu_has(cpu, X86_FEATURE_OSVW)) {
1162-
u64 osvw_len;
1163-
1164-
rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len);
1165-
if (osvw_id < osvw_len) {
1166-
u64 osvw_bits;
1167-
1168-
rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6),
1169-
osvw_bits);
1170-
return osvw_bits & (1ULL << (osvw_id & 0x3f));
1171-
}
1172-
}
1173-
1174-
/* OSVW unavailable or ID unknown, match family-model-stepping range */
1175-
ms = (cpu->x86_model << 4) | cpu->x86_stepping;
1176-
while ((range = *erratum++))
1177-
if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) &&
1178-
(ms >= AMD_MODEL_RANGE_START(range)) &&
1179-
(ms <= AMD_MODEL_RANGE_END(range)))
1180-
return true;
1181-
1182-
return false;
1183-
}
1184-
11851180
static DEFINE_PER_CPU_READ_MOSTLY(unsigned long[4], amd_dr_addr_mask);
11861181

11871182
static unsigned int amd_msr_dr_addr_masks[] = {

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