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Taniya Dasbebarino
Taniya Das
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bebarino
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dt-bindings: clock: Add sc7180 GCC clock binding
Add device tree bindings for global clock subsystem clock controller for Qualcomm Technology Inc's SC7180 SoCs. Signed-off-by: Taniya Das <[email protected]> Link: https://lkml.kernel.org/r/[email protected] Reviewed-by: Rob Herring <[email protected]> [[email protected]: Reword subject to make sc7180 specific, sort compatible] Signed-off-by: Stephen Boyd <[email protected]>
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‎Documentation/devicetree/bindings/clock/qcom,gcc.yaml

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@@ -33,6 +33,7 @@ properties:
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- qcom,gcc-msm8998
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- qcom,gcc-mdm9615
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- qcom,gcc-qcs404
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- qcom,gcc-sc7180
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- qcom,gcc-sdm630
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- qcom,gcc-sdm660
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- qcom,gcc-sdm845
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contains:
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enum:
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- qcom,gcc-sm8150
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- qcom,gcc-sc7180
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then:
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required:
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- clocks
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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# Example of GCC with clock nodes properties for SC7180:
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- |
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clock-controller@100000 {
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compatible = "qcom,gcc-sc7180";
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reg = <0x100000 0x1f0000>;
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clocks = <&rpmhcc 0>, <&rpmhcc 1>;
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clock-names = "bi_tcxo", "bi_tcxo_ao";
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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‎include/dt-bindings/clock/qcom,gcc-sc7180.h

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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2019, The Linux Foundation. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SC7180_H
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#define _DT_BINDINGS_CLK_QCOM_GCC_SC7180_H
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/* GCC clocks */
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#define GCC_GPLL0_MAIN_DIV_CDIV 0
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#define GPLL0 1
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#define GPLL0_OUT_EVEN 2
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#define GPLL1 3
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#define GPLL4 4
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#define GPLL6 5
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#define GPLL7 6
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#define GCC_AGGRE_UFS_PHY_AXI_CLK 7
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#define GCC_AGGRE_USB3_PRIM_AXI_CLK 8
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#define GCC_BOOT_ROM_AHB_CLK 9
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#define GCC_CAMERA_AHB_CLK 10
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#define GCC_CAMERA_HF_AXI_CLK 11
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#define GCC_CAMERA_THROTTLE_HF_AXI_CLK 12
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#define GCC_CAMERA_XO_CLK 13
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#define GCC_CE1_AHB_CLK 14
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#define GCC_CE1_AXI_CLK 15
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#define GCC_CE1_CLK 16
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#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 17
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#define GCC_CPUSS_AHB_CLK 18
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#define GCC_CPUSS_AHB_CLK_SRC 19
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#define GCC_CPUSS_GNOC_CLK 20
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#define GCC_CPUSS_RBCPR_CLK 21
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#define GCC_DDRSS_GPU_AXI_CLK 22
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#define GCC_DISP_AHB_CLK 23
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#define GCC_DISP_GPLL0_CLK_SRC 24
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#define GCC_DISP_GPLL0_DIV_CLK_SRC 25
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#define GCC_DISP_HF_AXI_CLK 26
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#define GCC_DISP_THROTTLE_HF_AXI_CLK 27
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#define GCC_DISP_XO_CLK 28
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#define GCC_GP1_CLK 29
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#define GCC_GP1_CLK_SRC 30
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#define GCC_GP2_CLK 31
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#define GCC_GP2_CLK_SRC 32
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#define GCC_GP3_CLK 33
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#define GCC_GP3_CLK_SRC 34
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#define GCC_GPU_CFG_AHB_CLK 35
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#define GCC_GPU_GPLL0_CLK_SRC 36
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#define GCC_GPU_GPLL0_DIV_CLK_SRC 37
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#define GCC_GPU_MEMNOC_GFX_CLK 38
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#define GCC_GPU_SNOC_DVM_GFX_CLK 39
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#define GCC_NPU_AXI_CLK 40
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#define GCC_NPU_BWMON_AXI_CLK 41
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#define GCC_NPU_BWMON_DMA_CFG_AHB_CLK 42
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#define GCC_NPU_BWMON_DSP_CFG_AHB_CLK 43
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#define GCC_NPU_CFG_AHB_CLK 44
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#define GCC_NPU_DMA_CLK 45
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#define GCC_NPU_GPLL0_CLK_SRC 46
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#define GCC_NPU_GPLL0_DIV_CLK_SRC 47
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#define GCC_PDM2_CLK 48
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#define GCC_PDM2_CLK_SRC 49
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#define GCC_PDM_AHB_CLK 50
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#define GCC_PDM_XO4_CLK 51
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#define GCC_PRNG_AHB_CLK 52
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#define GCC_QSPI_CNOC_PERIPH_AHB_CLK 53
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#define GCC_QSPI_CORE_CLK 54
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#define GCC_QSPI_CORE_CLK_SRC 55
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#define GCC_QUPV3_WRAP0_CORE_2X_CLK 56
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#define GCC_QUPV3_WRAP0_CORE_CLK 57
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#define GCC_QUPV3_WRAP0_S0_CLK 58
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#define GCC_QUPV3_WRAP0_S0_CLK_SRC 59
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#define GCC_QUPV3_WRAP0_S1_CLK 60
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#define GCC_QUPV3_WRAP0_S1_CLK_SRC 61
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#define GCC_QUPV3_WRAP0_S2_CLK 62
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#define GCC_QUPV3_WRAP0_S2_CLK_SRC 63
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#define GCC_QUPV3_WRAP0_S3_CLK 64
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#define GCC_QUPV3_WRAP0_S3_CLK_SRC 65
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#define GCC_QUPV3_WRAP0_S4_CLK 66
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#define GCC_QUPV3_WRAP0_S4_CLK_SRC 67
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#define GCC_QUPV3_WRAP0_S5_CLK 68
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#define GCC_QUPV3_WRAP0_S5_CLK_SRC 69
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#define GCC_QUPV3_WRAP1_CORE_2X_CLK 70
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#define GCC_QUPV3_WRAP1_CORE_CLK 71
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#define GCC_QUPV3_WRAP1_S0_CLK 72
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#define GCC_QUPV3_WRAP1_S0_CLK_SRC 73
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#define GCC_QUPV3_WRAP1_S1_CLK 74
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#define GCC_QUPV3_WRAP1_S1_CLK_SRC 75
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#define GCC_QUPV3_WRAP1_S2_CLK 76
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#define GCC_QUPV3_WRAP1_S2_CLK_SRC 77
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#define GCC_QUPV3_WRAP1_S3_CLK 78
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#define GCC_QUPV3_WRAP1_S3_CLK_SRC 79
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#define GCC_QUPV3_WRAP1_S4_CLK 80
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#define GCC_QUPV3_WRAP1_S4_CLK_SRC 81
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#define GCC_QUPV3_WRAP1_S5_CLK 82
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#define GCC_QUPV3_WRAP1_S5_CLK_SRC 83
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#define GCC_QUPV3_WRAP_0_M_AHB_CLK 84
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#define GCC_QUPV3_WRAP_0_S_AHB_CLK 85
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#define GCC_QUPV3_WRAP_1_M_AHB_CLK 86
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#define GCC_QUPV3_WRAP_1_S_AHB_CLK 87
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#define GCC_SDCC1_AHB_CLK 88
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#define GCC_SDCC1_APPS_CLK 89
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#define GCC_SDCC1_APPS_CLK_SRC 90
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#define GCC_SDCC1_ICE_CORE_CLK 91
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#define GCC_SDCC1_ICE_CORE_CLK_SRC 92
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#define GCC_SDCC2_AHB_CLK 93
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#define GCC_SDCC2_APPS_CLK 94
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#define GCC_SDCC2_APPS_CLK_SRC 95
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#define GCC_SYS_NOC_CPUSS_AHB_CLK 96
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#define GCC_UFS_MEM_CLKREF_CLK 97
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#define GCC_UFS_PHY_AHB_CLK 98
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#define GCC_UFS_PHY_AXI_CLK 99
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#define GCC_UFS_PHY_AXI_CLK_SRC 100
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#define GCC_UFS_PHY_ICE_CORE_CLK 101
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#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 102
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#define GCC_UFS_PHY_PHY_AUX_CLK 103
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#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 104
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#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 105
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#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 106
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#define GCC_UFS_PHY_UNIPRO_CORE_CLK 107
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#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 108
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#define GCC_USB30_PRIM_MASTER_CLK 109
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#define GCC_USB30_PRIM_MASTER_CLK_SRC 110
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#define GCC_USB30_PRIM_MOCK_UTMI_CLK 111
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#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 112
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#define GCC_USB30_PRIM_SLEEP_CLK 113
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#define GCC_USB3_PRIM_CLKREF_CLK 114
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#define GCC_USB3_PRIM_PHY_AUX_CLK 115
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#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 116
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#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 117
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#define GCC_USB3_PRIM_PHY_PIPE_CLK 118
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#define GCC_USB_PHY_CFG_AHB2PHY_CLK 119
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#define GCC_VIDEO_AHB_CLK 120
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#define GCC_VIDEO_AXI_CLK 121
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#define GCC_VIDEO_GPLL0_DIV_CLK_SRC 122
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#define GCC_VIDEO_THROTTLE_AXI_CLK 123
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#define GCC_VIDEO_XO_CLK 124
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/* GCC resets */
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#define GCC_QUSB2PHY_PRIM_BCR 0
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#define GCC_QUSB2PHY_SEC_BCR 1
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#define GCC_UFS_PHY_BCR 2
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#define GCC_USB30_PRIM_BCR 3
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#define GCC_USB3_DP_PHY_PRIM_BCR 4
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#define GCC_USB3_DP_PHY_SEC_BCR 5
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#define GCC_USB3_PHY_PRIM_BCR 6
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#define GCC_USB3_PHY_SEC_BCR 7
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#define GCC_USB3PHY_PHY_PRIM_BCR 8
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#define GCC_USB3PHY_PHY_SEC_BCR 9
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#define GCC_USB_PHY_CFG_AHB2PHY_BCR 10
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/* GCC GDSCRs */
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#define UFS_PHY_GDSC 0
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#define USB30_PRIM_GDSC 1
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#define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC 2
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#define HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC 3
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#endif

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