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Yongqiang NiuChun-Kuang Hu
Yongqiang Niu
authored and
Chun-Kuang Hu
committed
drm/mediatek: Add component POSTMASK
This patch add component POSTMASK. Signed-off-by: Yongqiang Niu <[email protected]> Signed-off-by: Hsin-Yi Wang <[email protected]> Signed-off-by: Chun-Kuang Hu <[email protected]>
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2 files changed

+73
-30
lines changed

2 files changed

+73
-30
lines changed

‎drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c

Lines changed: 72 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -60,6 +60,12 @@
6060
#define DITHER_ADD_LSHIFT_G(x) (((x) & 0x7) << 4)
6161
#define DITHER_ADD_RSHIFT_G(x) (((x) & 0x7) << 0)
6262

63+
#define DISP_POSTMASK_EN 0x0000
64+
#define POSTMASK_EN BIT(0)
65+
#define DISP_POSTMASK_CFG 0x0020
66+
#define POSTMASK_RELAY_MODE BIT(0)
67+
#define DISP_POSTMASK_SIZE 0x0030
68+
6369
struct mtk_ddp_comp_dev {
6470
struct clk *clk;
6571
void __iomem *regs;
@@ -211,6 +217,32 @@ static void mtk_dither_stop(struct device *dev)
211217
writel_relaxed(0x0, priv->regs + DISP_DITHER_EN);
212218
}
213219

220+
static void mtk_postmask_config(struct device *dev, unsigned int w,
221+
unsigned int h, unsigned int vrefresh,
222+
unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
223+
{
224+
struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
225+
226+
mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs,
227+
DISP_POSTMASK_SIZE);
228+
mtk_ddp_write(cmdq_pkt, POSTMASK_RELAY_MODE, &priv->cmdq_reg,
229+
priv->regs, DISP_POSTMASK_CFG);
230+
}
231+
232+
static void mtk_postmask_start(struct device *dev)
233+
{
234+
struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
235+
236+
writel(POSTMASK_EN, priv->regs + DISP_POSTMASK_EN);
237+
}
238+
239+
static void mtk_postmask_stop(struct device *dev)
240+
{
241+
struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
242+
243+
writel_relaxed(0x0, priv->regs + DISP_POSTMASK_EN);
244+
}
245+
214246
static const struct mtk_ddp_comp_funcs ddp_aal = {
215247
.clk_enable = mtk_aal_clk_enable,
216248
.clk_disable = mtk_aal_clk_disable,
@@ -286,6 +318,14 @@ static const struct mtk_ddp_comp_funcs ddp_ovl = {
286318
.bgclr_in_off = mtk_ovl_bgclr_in_off,
287319
};
288320

321+
static const struct mtk_ddp_comp_funcs ddp_postmask = {
322+
.clk_enable = mtk_ddp_clk_enable,
323+
.clk_disable = mtk_ddp_clk_disable,
324+
.config = mtk_postmask_config,
325+
.start = mtk_postmask_start,
326+
.stop = mtk_postmask_stop,
327+
};
328+
289329
static const struct mtk_ddp_comp_funcs ddp_rdma = {
290330
.clk_enable = mtk_rdma_clk_enable,
291331
.clk_disable = mtk_rdma_clk_disable,
@@ -321,6 +361,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
321361
[MTK_DISP_MUTEX] = "mutex",
322362
[MTK_DISP_OD] = "od",
323363
[MTK_DISP_BLS] = "bls",
364+
[MTK_DISP_POSTMASK] = "postmask",
324365
};
325366

326367
struct mtk_ddp_comp_match {
@@ -330,36 +371,37 @@ struct mtk_ddp_comp_match {
330371
};
331372

332373
static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
333-
[DDP_COMPONENT_AAL0] = { MTK_DISP_AAL, 0, &ddp_aal },
334-
[DDP_COMPONENT_AAL1] = { MTK_DISP_AAL, 1, &ddp_aal },
335-
[DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL },
336-
[DDP_COMPONENT_CCORR] = { MTK_DISP_CCORR, 0, &ddp_ccorr },
337-
[DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, &ddp_color },
338-
[DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, &ddp_color },
339-
[DDP_COMPONENT_DITHER] = { MTK_DISP_DITHER, 0, &ddp_dither },
340-
[DDP_COMPONENT_DPI0] = { MTK_DPI, 0, &ddp_dpi },
341-
[DDP_COMPONENT_DPI1] = { MTK_DPI, 1, &ddp_dpi },
342-
[DDP_COMPONENT_DSI0] = { MTK_DSI, 0, &ddp_dsi },
343-
[DDP_COMPONENT_DSI1] = { MTK_DSI, 1, &ddp_dsi },
344-
[DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi },
345-
[DDP_COMPONENT_DSI3] = { MTK_DSI, 3, &ddp_dsi },
346-
[DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma },
347-
[DDP_COMPONENT_OD0] = { MTK_DISP_OD, 0, &ddp_od },
348-
[DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od },
349-
[DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, &ddp_ovl },
350-
[DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, &ddp_ovl },
351-
[DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, &ddp_ovl },
352-
[DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, &ddp_ovl },
353-
[DDP_COMPONENT_OVL_2L2] = { MTK_DISP_OVL_2L, 2, &ddp_ovl },
354-
[DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL },
355-
[DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL },
356-
[DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL },
357-
[DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, &ddp_rdma },
358-
[DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, &ddp_rdma },
359-
[DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, &ddp_rdma },
360-
[DDP_COMPONENT_UFOE] = { MTK_DISP_UFOE, 0, &ddp_ufoe },
361-
[DDP_COMPONENT_WDMA0] = { MTK_DISP_WDMA, 0, NULL },
362-
[DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, NULL },
374+
[DDP_COMPONENT_AAL0] = { MTK_DISP_AAL, 0, &ddp_aal },
375+
[DDP_COMPONENT_AAL1] = { MTK_DISP_AAL, 1, &ddp_aal },
376+
[DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL },
377+
[DDP_COMPONENT_CCORR] = { MTK_DISP_CCORR, 0, &ddp_ccorr },
378+
[DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, &ddp_color },
379+
[DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, &ddp_color },
380+
[DDP_COMPONENT_DITHER] = { MTK_DISP_DITHER, 0, &ddp_dither },
381+
[DDP_COMPONENT_DPI0] = { MTK_DPI, 0, &ddp_dpi },
382+
[DDP_COMPONENT_DPI1] = { MTK_DPI, 1, &ddp_dpi },
383+
[DDP_COMPONENT_DSI0] = { MTK_DSI, 0, &ddp_dsi },
384+
[DDP_COMPONENT_DSI1] = { MTK_DSI, 1, &ddp_dsi },
385+
[DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi },
386+
[DDP_COMPONENT_DSI3] = { MTK_DSI, 3, &ddp_dsi },
387+
[DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma },
388+
[DDP_COMPONENT_OD0] = { MTK_DISP_OD, 0, &ddp_od },
389+
[DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od },
390+
[DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, &ddp_ovl },
391+
[DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, &ddp_ovl },
392+
[DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, &ddp_ovl },
393+
[DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, &ddp_ovl },
394+
[DDP_COMPONENT_OVL_2L2] = { MTK_DISP_OVL_2L, 2, &ddp_ovl },
395+
[DDP_COMPONENT_POSTMASK0] = { MTK_DISP_POSTMASK, 0, &ddp_postmask },
396+
[DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL },
397+
[DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL },
398+
[DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL },
399+
[DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, &ddp_rdma },
400+
[DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, &ddp_rdma },
401+
[DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, &ddp_rdma },
402+
[DDP_COMPONENT_UFOE] = { MTK_DISP_UFOE, 0, &ddp_ufoe },
403+
[DDP_COMPONENT_WDMA0] = { MTK_DISP_WDMA, 0, NULL },
404+
[DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, NULL },
363405
};
364406

365407
static bool mtk_drm_find_comp_in_ddp(struct device *dev,

‎drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -30,6 +30,7 @@ enum mtk_ddp_comp_type {
3030
MTK_DISP_UFOE,
3131
MTK_DSI,
3232
MTK_DPI,
33+
MTK_DISP_POSTMASK,
3334
MTK_DISP_PWM,
3435
MTK_DISP_MUTEX,
3536
MTK_DISP_OD,

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