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| 1 | +// SPDX-License-Identifier: MIT |
| 2 | +/* |
| 3 | + * Copyright © 2023 Intel Corporation |
| 4 | + */ |
| 5 | + |
| 6 | +#include "i915_drv.h" |
| 7 | + |
| 8 | +#include "intel_atomic.h" |
| 9 | +#include "intel_display_types.h" |
| 10 | +#include "intel_link_bw.h" |
| 11 | + |
| 12 | +/** |
| 13 | + * intel_link_bw_init_limits - initialize BW limits |
| 14 | + * @i915: device instance |
| 15 | + * @limits: link BW limits |
| 16 | + * |
| 17 | + * Initialize @limits. |
| 18 | + */ |
| 19 | +void intel_link_bw_init_limits(struct drm_i915_private *i915, struct intel_link_bw_limits *limits) |
| 20 | +{ |
| 21 | + enum pipe pipe; |
| 22 | + |
| 23 | + limits->bpp_limit_reached_pipes = 0; |
| 24 | + for_each_pipe(i915, pipe) |
| 25 | + limits->max_bpp_x16[pipe] = INT_MAX; |
| 26 | +} |
| 27 | + |
| 28 | +/** |
| 29 | + * intel_link_bw_reduce_bpp - reduce maximum link bpp for a selected pipe |
| 30 | + * @state: atomic state |
| 31 | + * @limits: link BW limits |
| 32 | + * @pipe_mask: mask of pipes to select from |
| 33 | + * @reason: explanation of why bpp reduction is needed |
| 34 | + * |
| 35 | + * Select the pipe from @pipe_mask with the biggest link bpp value and set the |
| 36 | + * maximum of link bpp in @limits below this value. Modeset the selected pipe, |
| 37 | + * so that its state will get recomputed. |
| 38 | + * |
| 39 | + * This function can be called to resolve a link's BW overallocation by reducing |
| 40 | + * the link bpp of one pipe on the link and hence reducing the total link BW. |
| 41 | + * |
| 42 | + * Returns |
| 43 | + * - 0 in case of success |
| 44 | + * - %-ENOSPC if no pipe can further reduce its link bpp |
| 45 | + * - Other negative error, if modesetting the selected pipe failed |
| 46 | + */ |
| 47 | +int intel_link_bw_reduce_bpp(struct intel_atomic_state *state, |
| 48 | + struct intel_link_bw_limits *limits, |
| 49 | + u8 pipe_mask, |
| 50 | + const char *reason) |
| 51 | +{ |
| 52 | + struct drm_i915_private *i915 = to_i915(state->base.dev); |
| 53 | + enum pipe max_bpp_pipe = INVALID_PIPE; |
| 54 | + struct intel_crtc *crtc; |
| 55 | + int max_bpp = 0; |
| 56 | + |
| 57 | + for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, pipe_mask) { |
| 58 | + struct intel_crtc_state *crtc_state; |
| 59 | + int link_bpp; |
| 60 | + |
| 61 | + if (limits->bpp_limit_reached_pipes & BIT(crtc->pipe)) |
| 62 | + continue; |
| 63 | + |
| 64 | + crtc_state = intel_atomic_get_crtc_state(&state->base, |
| 65 | + crtc); |
| 66 | + if (IS_ERR(crtc_state)) |
| 67 | + return PTR_ERR(crtc_state); |
| 68 | + |
| 69 | + if (crtc_state->dsc.compression_enable) |
| 70 | + link_bpp = crtc_state->dsc.compressed_bpp; |
| 71 | + else |
| 72 | + /* |
| 73 | + * TODO: for YUV420 the actual link bpp is only half |
| 74 | + * of the pipe bpp value. The MST encoder's BW allocation |
| 75 | + * is based on the pipe bpp value, set the actual link bpp |
| 76 | + * limit here once the MST BW allocation is fixed. |
| 77 | + */ |
| 78 | + link_bpp = crtc_state->pipe_bpp; |
| 79 | + |
| 80 | + if (link_bpp > max_bpp) { |
| 81 | + max_bpp = link_bpp; |
| 82 | + max_bpp_pipe = crtc->pipe; |
| 83 | + } |
| 84 | + } |
| 85 | + |
| 86 | + if (max_bpp_pipe == INVALID_PIPE) |
| 87 | + return -ENOSPC; |
| 88 | + |
| 89 | + limits->max_bpp_x16[max_bpp_pipe] = to_bpp_x16(max_bpp) - 1; |
| 90 | + |
| 91 | + return intel_modeset_pipes_in_mask_early(state, reason, |
| 92 | + BIT(max_bpp_pipe)); |
| 93 | +} |
| 94 | + |
| 95 | +/** |
| 96 | + * intel_link_bw_set_bpp_limit_for_pipe - set link bpp limit for a pipe to its minimum |
| 97 | + * @state: atomic state |
| 98 | + * @old_limits: link BW limits |
| 99 | + * @new_limits: link BW limits |
| 100 | + * @pipe: pipe |
| 101 | + * |
| 102 | + * Set the link bpp limit for @pipe in @new_limits to its value in |
| 103 | + * @old_limits and mark this limit as the minimum. This function must be |
| 104 | + * called after a pipe's compute config function failed, @old_limits |
| 105 | + * containing the bpp limit with which compute config previously passed. |
| 106 | + * |
| 107 | + * The function will fail if setting a minimum is not possible, either |
| 108 | + * because the old and new limits match (and so would lead to a pipe compute |
| 109 | + * config failure) or the limit is already at the minimum. |
| 110 | + * |
| 111 | + * Returns %true in case of success. |
| 112 | + */ |
| 113 | +bool |
| 114 | +intel_link_bw_set_bpp_limit_for_pipe(struct intel_atomic_state *state, |
| 115 | + const struct intel_link_bw_limits *old_limits, |
| 116 | + struct intel_link_bw_limits *new_limits, |
| 117 | + enum pipe pipe) |
| 118 | +{ |
| 119 | + struct drm_i915_private *i915 = to_i915(state->base.dev); |
| 120 | + |
| 121 | + if (pipe == INVALID_PIPE) |
| 122 | + return false; |
| 123 | + |
| 124 | + if (new_limits->max_bpp_x16[pipe] == |
| 125 | + old_limits->max_bpp_x16[pipe]) |
| 126 | + return false; |
| 127 | + |
| 128 | + if (drm_WARN_ON(&i915->drm, |
| 129 | + new_limits->bpp_limit_reached_pipes & BIT(pipe))) |
| 130 | + return false; |
| 131 | + |
| 132 | + new_limits->max_bpp_x16[pipe] = |
| 133 | + old_limits->max_bpp_x16[pipe]; |
| 134 | + new_limits->bpp_limit_reached_pipes |= BIT(pipe); |
| 135 | + |
| 136 | + return true; |
| 137 | +} |
| 138 | + |
| 139 | +static int check_all_link_config(struct intel_atomic_state *state, |
| 140 | + struct intel_link_bw_limits *limits) |
| 141 | +{ |
| 142 | + /* TODO: Check all shared display link configurations like FDI */ |
| 143 | + return 0; |
| 144 | +} |
| 145 | + |
| 146 | +static bool |
| 147 | +assert_link_limit_change_valid(struct drm_i915_private *i915, |
| 148 | + const struct intel_link_bw_limits *old_limits, |
| 149 | + const struct intel_link_bw_limits *new_limits) |
| 150 | +{ |
| 151 | + bool bpps_changed = false; |
| 152 | + enum pipe pipe; |
| 153 | + |
| 154 | + for_each_pipe(i915, pipe) { |
| 155 | + /* The bpp limit can only decrease. */ |
| 156 | + if (drm_WARN_ON(&i915->drm, |
| 157 | + new_limits->max_bpp_x16[pipe] > |
| 158 | + old_limits->max_bpp_x16[pipe])) |
| 159 | + return false; |
| 160 | + |
| 161 | + if (new_limits->max_bpp_x16[pipe] < |
| 162 | + old_limits->max_bpp_x16[pipe]) |
| 163 | + bpps_changed = true; |
| 164 | + } |
| 165 | + |
| 166 | + /* At least one limit must change. */ |
| 167 | + if (drm_WARN_ON(&i915->drm, |
| 168 | + !bpps_changed)) |
| 169 | + return false; |
| 170 | + |
| 171 | + return true; |
| 172 | +} |
| 173 | + |
| 174 | +/** |
| 175 | + * intel_link_bw_atomic_check - check display link states and set a fallback config if needed |
| 176 | + * @state: atomic state |
| 177 | + * @new_limits: link BW limits |
| 178 | + * |
| 179 | + * Check the configuration of all shared display links in @state and set new BW |
| 180 | + * limits in @new_limits if there is a BW limitation. |
| 181 | + * |
| 182 | + * Returns: |
| 183 | + * - 0 if the confugration is valid |
| 184 | + * - %-EAGAIN, if the configuration is invalid and @new_limits got updated |
| 185 | + * with fallback values with which the configuration of all CRTCs |
| 186 | + * in @state must be recomputed |
| 187 | + * - Other negative error, if the configuration is invalid without a |
| 188 | + * fallback possibility, or the check failed for another reason |
| 189 | + */ |
| 190 | +int intel_link_bw_atomic_check(struct intel_atomic_state *state, |
| 191 | + struct intel_link_bw_limits *new_limits) |
| 192 | +{ |
| 193 | + struct drm_i915_private *i915 = to_i915(state->base.dev); |
| 194 | + struct intel_link_bw_limits old_limits = *new_limits; |
| 195 | + int ret; |
| 196 | + |
| 197 | + ret = check_all_link_config(state, new_limits); |
| 198 | + if (ret != -EAGAIN) |
| 199 | + return ret; |
| 200 | + |
| 201 | + if (!assert_link_limit_change_valid(i915, &old_limits, new_limits)) |
| 202 | + return -EINVAL; |
| 203 | + |
| 204 | + return -EAGAIN; |
| 205 | +} |
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