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Merge tag 'sunxi-clk-for-5.7' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner
Pull Allwinner clk driver updates from Chen-Yu Tsai: Changes consist mainly of cleanups for the display engine clock driver, correcting clocks that don't exist. Also, the MBUS clock on the A64 is exported for the device tree to consume. * tag 'sunxi-clk-for-5.7' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: clk: sunxi-ng: sun8i-de2: Sort structures clk: sunxi-ng: sun8i-de2: Add R40 specific quirks clk: sunxi-ng: sun8i-de2: Add rotation core clocks and reset for A83T clk: sunxi-ng: sun8i-de2: Don't reuse A83T resets clk: sunxi-ng: sun8i-de2: H6 doesn't have rotate core clk: sunxi-ng: sun8i-de2: Add rotation core clocks and reset for A64 clk: sunxi-ng: sun8i-de2: Split out H5 definitions clk: sunxi-ng: a64: Export MBUS clock
2 parents bb6d3fb + b998b75 commit 8ca1f3c

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‎drivers/clk/sunxi-ng/ccu-sun50i-a64.h

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -55,10 +55,6 @@
5555

5656
/* All the DRAM gates are exported */
5757

58-
/* Some more module clocks are exported */
59-
60-
#define CLK_MBUS 112
61-
6258
/* And the DSI and GPU module clock is exported */
6359

6460
#define CLK_NUMBER (CLK_GPU + 1)

‎drivers/clk/sunxi-ng/ccu-sun8i-de2.c

Lines changed: 74 additions & 41 deletions
Original file line numberDiff line numberDiff line change
@@ -50,8 +50,10 @@ static SUNXI_CCU_M(mixer1_div_a83_clk, "mixer1-div", "pll-de", 0x0c, 4, 4,
5050
CLK_SET_RATE_PARENT);
5151
static SUNXI_CCU_M(wb_div_a83_clk, "wb-div", "pll-de", 0x0c, 8, 4,
5252
CLK_SET_RATE_PARENT);
53+
static SUNXI_CCU_M(rot_div_a83_clk, "rot-div", "pll-de", 0x0c, 0x0c, 4,
54+
CLK_SET_RATE_PARENT);
5355

54-
static struct ccu_common *sun50i_h6_de3_clks[] = {
56+
static struct ccu_common *sun8i_a83t_de2_clks[] = {
5557
&mixer0_clk.common,
5658
&mixer1_clk.common,
5759
&wb_clk.common,
@@ -60,16 +62,16 @@ static struct ccu_common *sun50i_h6_de3_clks[] = {
6062
&bus_mixer1_clk.common,
6163
&bus_wb_clk.common,
6264

63-
&mixer0_div_clk.common,
64-
&mixer1_div_clk.common,
65-
&wb_div_clk.common,
65+
&mixer0_div_a83_clk.common,
66+
&mixer1_div_a83_clk.common,
67+
&wb_div_a83_clk.common,
6668

6769
&bus_rot_clk.common,
6870
&rot_clk.common,
69-
&rot_div_clk.common,
71+
&rot_div_a83_clk.common,
7072
};
7173

72-
static struct ccu_common *sun8i_a83t_de2_clks[] = {
74+
static struct ccu_common *sun8i_h3_de2_clks[] = {
7375
&mixer0_clk.common,
7476
&mixer1_clk.common,
7577
&wb_clk.common,
@@ -78,51 +80,58 @@ static struct ccu_common *sun8i_a83t_de2_clks[] = {
7880
&bus_mixer1_clk.common,
7981
&bus_wb_clk.common,
8082

81-
&mixer0_div_a83_clk.common,
82-
&mixer1_div_a83_clk.common,
83-
&wb_div_a83_clk.common,
83+
&mixer0_div_clk.common,
84+
&mixer1_div_clk.common,
85+
&wb_div_clk.common,
8486
};
8587

86-
static struct ccu_common *sun8i_h3_de2_clks[] = {
88+
static struct ccu_common *sun8i_v3s_de2_clks[] = {
8789
&mixer0_clk.common,
88-
&mixer1_clk.common,
8990
&wb_clk.common,
9091

9192
&bus_mixer0_clk.common,
92-
&bus_mixer1_clk.common,
9393
&bus_wb_clk.common,
9494

9595
&mixer0_div_clk.common,
96-
&mixer1_div_clk.common,
9796
&wb_div_clk.common,
9897
};
9998

100-
static struct ccu_common *sun8i_v3s_de2_clks[] = {
99+
static struct ccu_common *sun50i_a64_de2_clks[] = {
101100
&mixer0_clk.common,
101+
&mixer1_clk.common,
102102
&wb_clk.common,
103103

104104
&bus_mixer0_clk.common,
105+
&bus_mixer1_clk.common,
105106
&bus_wb_clk.common,
106107

107108
&mixer0_div_clk.common,
109+
&mixer1_div_clk.common,
108110
&wb_div_clk.common,
111+
112+
&bus_rot_clk.common,
113+
&rot_clk.common,
114+
&rot_div_clk.common,
109115
};
110116

111117
static struct clk_hw_onecell_data sun8i_a83t_de2_hw_clks = {
112118
.hws = {
113119
[CLK_MIXER0] = &mixer0_clk.common.hw,
114120
[CLK_MIXER1] = &mixer1_clk.common.hw,
115121
[CLK_WB] = &wb_clk.common.hw,
122+
[CLK_ROT] = &rot_clk.common.hw,
116123

117124
[CLK_BUS_MIXER0] = &bus_mixer0_clk.common.hw,
118125
[CLK_BUS_MIXER1] = &bus_mixer1_clk.common.hw,
119126
[CLK_BUS_WB] = &bus_wb_clk.common.hw,
127+
[CLK_BUS_ROT] = &bus_rot_clk.common.hw,
120128

121129
[CLK_MIXER0_DIV] = &mixer0_div_a83_clk.common.hw,
122130
[CLK_MIXER1_DIV] = &mixer1_div_a83_clk.common.hw,
123131
[CLK_WB_DIV] = &wb_div_a83_clk.common.hw,
132+
[CLK_ROT_DIV] = &rot_div_a83_clk.common.hw,
124133
},
125-
.num = CLK_NUMBER_WITHOUT_ROT,
134+
.num = CLK_NUMBER_WITH_ROT,
126135
};
127136

128137
static struct clk_hw_onecell_data sun8i_h3_de2_hw_clks = {
@@ -156,7 +165,7 @@ static struct clk_hw_onecell_data sun8i_v3s_de2_hw_clks = {
156165
.num = CLK_NUMBER_WITHOUT_ROT,
157166
};
158167

159-
static struct clk_hw_onecell_data sun50i_h6_de3_hw_clks = {
168+
static struct clk_hw_onecell_data sun50i_a64_de2_hw_clks = {
160169
.hws = {
161170
[CLK_MIXER0] = &mixer0_clk.common.hw,
162171
[CLK_MIXER1] = &mixer1_clk.common.hw,
@@ -179,9 +188,19 @@ static struct clk_hw_onecell_data sun50i_h6_de3_hw_clks = {
179188
static struct ccu_reset_map sun8i_a83t_de2_resets[] = {
180189
[RST_MIXER0] = { 0x08, BIT(0) },
181190
/*
182-
* For A83T, H3 and R40, mixer1 reset line is shared with wb, so
183-
* only RST_WB is exported here.
184-
* For V3s there's just no mixer1, so it also shares this struct.
191+
* Mixer1 reset line is shared with wb, so only RST_WB is
192+
* exported here.
193+
*/
194+
[RST_WB] = { 0x08, BIT(2) },
195+
[RST_ROT] = { 0x08, BIT(3) },
196+
};
197+
198+
static struct ccu_reset_map sun8i_h3_de2_resets[] = {
199+
[RST_MIXER0] = { 0x08, BIT(0) },
200+
/*
201+
* Mixer1 reset line is shared with wb, so only RST_WB is
202+
* exported here.
203+
* V3s doesn't have mixer1, so it also shares this struct.
185204
*/
186205
[RST_WB] = { 0x08, BIT(2) },
187206
};
@@ -190,13 +209,13 @@ static struct ccu_reset_map sun50i_a64_de2_resets[] = {
190209
[RST_MIXER0] = { 0x08, BIT(0) },
191210
[RST_MIXER1] = { 0x08, BIT(1) },
192211
[RST_WB] = { 0x08, BIT(2) },
212+
[RST_ROT] = { 0x08, BIT(3) },
193213
};
194214

195-
static struct ccu_reset_map sun50i_h6_de3_resets[] = {
215+
static struct ccu_reset_map sun50i_h5_de2_resets[] = {
196216
[RST_MIXER0] = { 0x08, BIT(0) },
197217
[RST_MIXER1] = { 0x08, BIT(1) },
198218
[RST_WB] = { 0x08, BIT(2) },
199-
[RST_ROT] = { 0x08, BIT(3) },
200219
};
201220

202221
static const struct sunxi_ccu_desc sun8i_a83t_de2_clk_desc = {
@@ -215,28 +234,18 @@ static const struct sunxi_ccu_desc sun8i_h3_de2_clk_desc = {
215234

216235
.hw_clks = &sun8i_h3_de2_hw_clks,
217236

218-
.resets = sun8i_a83t_de2_resets,
219-
.num_resets = ARRAY_SIZE(sun8i_a83t_de2_resets),
237+
.resets = sun8i_h3_de2_resets,
238+
.num_resets = ARRAY_SIZE(sun8i_h3_de2_resets),
220239
};
221240

222-
static const struct sunxi_ccu_desc sun50i_a64_de2_clk_desc = {
223-
.ccu_clks = sun8i_h3_de2_clks,
224-
.num_ccu_clks = ARRAY_SIZE(sun8i_h3_de2_clks),
241+
static const struct sunxi_ccu_desc sun8i_r40_de2_clk_desc = {
242+
.ccu_clks = sun50i_a64_de2_clks,
243+
.num_ccu_clks = ARRAY_SIZE(sun50i_a64_de2_clks),
225244

226-
.hw_clks = &sun8i_h3_de2_hw_clks,
245+
.hw_clks = &sun50i_a64_de2_hw_clks,
227246

228-
.resets = sun50i_a64_de2_resets,
229-
.num_resets = ARRAY_SIZE(sun50i_a64_de2_resets),
230-
};
231-
232-
static const struct sunxi_ccu_desc sun50i_h6_de3_clk_desc = {
233-
.ccu_clks = sun50i_h6_de3_clks,
234-
.num_ccu_clks = ARRAY_SIZE(sun50i_h6_de3_clks),
235-
236-
.hw_clks = &sun50i_h6_de3_hw_clks,
237-
238-
.resets = sun50i_h6_de3_resets,
239-
.num_resets = ARRAY_SIZE(sun50i_h6_de3_resets),
247+
.resets = sun8i_a83t_de2_resets,
248+
.num_resets = ARRAY_SIZE(sun8i_a83t_de2_resets),
240249
};
241250

242251
static const struct sunxi_ccu_desc sun8i_v3s_de2_clk_desc = {
@@ -249,6 +258,26 @@ static const struct sunxi_ccu_desc sun8i_v3s_de2_clk_desc = {
249258
.num_resets = ARRAY_SIZE(sun8i_a83t_de2_resets),
250259
};
251260

261+
static const struct sunxi_ccu_desc sun50i_a64_de2_clk_desc = {
262+
.ccu_clks = sun50i_a64_de2_clks,
263+
.num_ccu_clks = ARRAY_SIZE(sun50i_a64_de2_clks),
264+
265+
.hw_clks = &sun50i_a64_de2_hw_clks,
266+
267+
.resets = sun50i_a64_de2_resets,
268+
.num_resets = ARRAY_SIZE(sun50i_a64_de2_resets),
269+
};
270+
271+
static const struct sunxi_ccu_desc sun50i_h5_de2_clk_desc = {
272+
.ccu_clks = sun8i_h3_de2_clks,
273+
.num_ccu_clks = ARRAY_SIZE(sun8i_h3_de2_clks),
274+
275+
.hw_clks = &sun8i_h3_de2_hw_clks,
276+
277+
.resets = sun50i_h5_de2_resets,
278+
.num_resets = ARRAY_SIZE(sun50i_h5_de2_resets),
279+
};
280+
252281
static int sunxi_de2_clk_probe(struct platform_device *pdev)
253282
{
254283
struct resource *res;
@@ -337,6 +366,10 @@ static const struct of_device_id sunxi_de2_clk_ids[] = {
337366
.compatible = "allwinner,sun8i-h3-de2-clk",
338367
.data = &sun8i_h3_de2_clk_desc,
339368
},
369+
{
370+
.compatible = "allwinner,sun8i-r40-de2-clk",
371+
.data = &sun8i_r40_de2_clk_desc,
372+
},
340373
{
341374
.compatible = "allwinner,sun8i-v3s-de2-clk",
342375
.data = &sun8i_v3s_de2_clk_desc,
@@ -347,11 +380,11 @@ static const struct of_device_id sunxi_de2_clk_ids[] = {
347380
},
348381
{
349382
.compatible = "allwinner,sun50i-h5-de2-clk",
350-
.data = &sun50i_a64_de2_clk_desc,
383+
.data = &sun50i_h5_de2_clk_desc,
351384
},
352385
{
353386
.compatible = "allwinner,sun50i-h6-de3-clk",
354-
.data = &sun50i_h6_de3_clk_desc,
387+
.data = &sun50i_h5_de2_clk_desc,
355388
},
356389
{ }
357390
};

‎include/dt-bindings/clock/sun50i-a64-ccu.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -131,7 +131,7 @@
131131
#define CLK_AVS 109
132132
#define CLK_HDMI 110
133133
#define CLK_HDMI_DDC 111
134-
134+
#define CLK_MBUS 112
135135
#define CLK_DSI_DPHY 113
136136
#define CLK_GPU 114
137137

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