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Anshuman Khandualctmarinas
Anshuman Khandual
authored and
ctmarinas
committed
arm64/cpufeature: Replace all open bits shift encodings with macros
There are many open bits shift encodings for various CPU ID registers that are scattered across cpufeature. This replaces them with register specific sensible macro definitions. This should not have any functional change. Signed-off-by: Anshuman Khandual <[email protected]> Reviewed-by: Suzuki K Poulose <[email protected]> Cc: Will Deacon <[email protected]> Cc: Marc Zyngier <[email protected]> Cc: Mark Rutland <[email protected]> Cc: James Morse <[email protected]> Cc: Suzuki K Poulose <[email protected]> Cc: [email protected] Cc: [email protected] Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Catalin Marinas <[email protected]>
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‎arch/arm64/include/asm/sysreg.h

Lines changed: 28 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -769,6 +769,7 @@
769769
#define ID_AA64MMFR2_CNP_SHIFT 0
770770

771771
/* id_aa64dfr0 */
772+
#define ID_AA64DFR0_DOUBLELOCK_SHIFT 36
772773
#define ID_AA64DFR0_PMSVER_SHIFT 32
773774
#define ID_AA64DFR0_CTX_CMPS_SHIFT 28
774775
#define ID_AA64DFR0_WRPS_SHIFT 20
@@ -821,18 +822,40 @@
821822
#define ID_ISAR6_DP_SHIFT 4
822823
#define ID_ISAR6_JSCVT_SHIFT 0
823824

825+
#define ID_MMFR0_INNERSHR_SHIFT 28
826+
#define ID_MMFR0_FCSE_SHIFT 24
827+
#define ID_MMFR0_AUXREG_SHIFT 20
828+
#define ID_MMFR0_TCM_SHIFT 16
829+
#define ID_MMFR0_SHARELVL_SHIFT 12
830+
#define ID_MMFR0_OUTERSHR_SHIFT 8
831+
#define ID_MMFR0_PMSA_SHIFT 4
832+
#define ID_MMFR0_VMSA_SHIFT 0
833+
824834
#define ID_MMFR4_EVT_SHIFT 28
825835
#define ID_MMFR4_CCIDX_SHIFT 24
826836
#define ID_MMFR4_LSM_SHIFT 20
827837
#define ID_MMFR4_HPDS_SHIFT 16
828838
#define ID_MMFR4_CNP_SHIFT 12
829839
#define ID_MMFR4_XNX_SHIFT 8
840+
#define ID_MMFR4_AC2_SHIFT 4
830841
#define ID_MMFR4_SPECSEI_SHIFT 0
831842

832843
#define ID_MMFR5_ETS_SHIFT 0
833844

834845
#define ID_PFR0_DIT_SHIFT 24
835846
#define ID_PFR0_CSV2_SHIFT 16
847+
#define ID_PFR0_STATE3_SHIFT 12
848+
#define ID_PFR0_STATE2_SHIFT 8
849+
#define ID_PFR0_STATE1_SHIFT 4
850+
#define ID_PFR0_STATE0_SHIFT 0
851+
852+
#define ID_DFR0_PERFMON_SHIFT 24
853+
#define ID_DFR0_MPROFDBG_SHIFT 20
854+
#define ID_DFR0_MMAPTRC_SHIFT 16
855+
#define ID_DFR0_COPTRC_SHIFT 12
856+
#define ID_DFR0_MMAPDBG_SHIFT 8
857+
#define ID_DFR0_COPSDBG_SHIFT 4
858+
#define ID_DFR0_COPDBG_SHIFT 0
836859

837860
#define ID_PFR2_SSBS_SHIFT 4
838861
#define ID_PFR2_CSV3_SHIFT 0
@@ -875,6 +898,11 @@
875898
#define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN64_SUPPORTED
876899
#endif
877900

901+
#define MVFR2_FPMISC_SHIFT 4
902+
#define MVFR2_SIMDMISC_SHIFT 0
903+
904+
#define DCZID_DZP_SHIFT 4
905+
#define DCZID_BS_SHIFT 0
878906

879907
/*
880908
* The ZCR_ELx_LEN_* definitions intentionally include bits [8:4] which

‎arch/arm64/kernel/cpufeature.c

Lines changed: 27 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -359,7 +359,7 @@ static const struct arm64_ftr_bits ftr_ctr[] = {
359359
* make use of *minLine.
360360
* If we have differing I-cache policies, report it as the weakest - VIPT.
361361
*/
362-
ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, 14, 2, ICACHE_POLICY_VIPT), /* L1Ip */
362+
ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, CTR_L1IP_SHIFT, 2, ICACHE_POLICY_VIPT), /* L1Ip */
363363
ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IMINLINE_SHIFT, 4, 0),
364364
ARM64_FTR_END,
365365
};
@@ -370,19 +370,19 @@ struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = {
370370
};
371371

372372
static const struct arm64_ftr_bits ftr_id_mmfr0[] = {
373-
S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0xf), /* InnerShr */
374-
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0), /* FCSE */
375-
ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 20, 4, 0), /* AuxReg */
376-
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), /* TCM */
377-
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), /* ShareLvl */
378-
S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0xf), /* OuterShr */
379-
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* PMSA */
380-
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* VMSA */
373+
S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_INNERSHR_SHIFT, 4, 0xf),
374+
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_FCSE_SHIFT, 4, 0),
375+
ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_MMFR0_AUXREG_SHIFT, 4, 0),
376+
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_TCM_SHIFT, 4, 0),
377+
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_SHARELVL_SHIFT, 4, 0),
378+
S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_OUTERSHR_SHIFT, 4, 0xf),
379+
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_PMSA_SHIFT, 4, 0),
380+
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_VMSA_SHIFT, 4, 0),
381381
ARM64_FTR_END,
382382
};
383383

384384
static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
385-
S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 36, 4, 0),
385+
S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_DOUBLELOCK_SHIFT, 4, 0),
386386
ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_PMSVER_SHIFT, 4, 0),
387387
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0),
388388
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0),
@@ -398,14 +398,14 @@ static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
398398
};
399399

400400
static const struct arm64_ftr_bits ftr_mvfr2[] = {
401-
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* FPMisc */
402-
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* SIMDMisc */
401+
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_FPMISC_SHIFT, 4, 0),
402+
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_SIMDMISC_SHIFT, 4, 0),
403403
ARM64_FTR_END,
404404
};
405405

406406
static const struct arm64_ftr_bits ftr_dczid[] = {
407-
ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 4, 1, 1), /* DZP */
408-
ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* BS */
407+
ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, DCZID_DZP_SHIFT, 1, 1),
408+
ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, DCZID_BS_SHIFT, 4, 0),
409409
ARM64_FTR_END,
410410
};
411411

@@ -437,7 +437,8 @@ static const struct arm64_ftr_bits ftr_id_mmfr4[] = {
437437
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_HPDS_SHIFT, 4, 0),
438438
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_CNP_SHIFT, 4, 0),
439439
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_XNX_SHIFT, 4, 0),
440-
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* ac2 */
440+
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_AC2_SHIFT, 4, 0),
441+
441442
/*
442443
* SpecSEI = 1 indicates that the PE might generate an SError on an
443444
* external abort on speculative read. It is safe to assume that an
@@ -479,10 +480,10 @@ static const struct arm64_ftr_bits ftr_id_isar6[] = {
479480
static const struct arm64_ftr_bits ftr_id_pfr0[] = {
480481
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_DIT_SHIFT, 4, 0),
481482
ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR0_CSV2_SHIFT, 4, 0),
482-
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), /* State3 */
483-
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), /* State2 */
484-
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* State1 */
485-
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* State0 */
483+
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE3_SHIFT, 4, 0),
484+
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE2_SHIFT, 4, 0),
485+
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE1_SHIFT, 4, 0),
486+
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE0_SHIFT, 4, 0),
486487
ARM64_FTR_END,
487488
};
488489

@@ -506,13 +507,13 @@ static const struct arm64_ftr_bits ftr_id_pfr2[] = {
506507

507508
static const struct arm64_ftr_bits ftr_id_dfr0[] = {
508509
/* [31:28] TraceFilt */
509-
S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0xf), /* PerfMon */
510-
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
511-
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
512-
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
513-
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
514-
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
515-
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
510+
S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_PERFMON_SHIFT, 4, 0xf),
511+
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MPROFDBG_SHIFT, 4, 0),
512+
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MMAPTRC_SHIFT, 4, 0),
513+
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPTRC_SHIFT, 4, 0),
514+
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MMAPDBG_SHIFT, 4, 0),
515+
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPSDBG_SHIFT, 4, 0),
516+
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPDBG_SHIFT, 4, 0),
516517
ARM64_FTR_END,
517518
};
518519

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