2424#include <linux/libata.h>
2525#include <linux/phy/phy.h>
2626#include <linux/regulator/consumer.h>
27+ #include <linux/bits.h>
2728
2829/* Enclosure Management Control */
2930#define EM_CTRL_MSG_TYPE 0x000f0000
@@ -53,12 +54,12 @@ enum {
5354 AHCI_PORT_PRIV_FBS_DMA_SZ = AHCI_CMD_SLOT_SZ +
5455 AHCI_CMD_TBL_AR_SZ +
5556 (AHCI_RX_FIS_SZ * 16 ),
56- AHCI_IRQ_ON_SG = ( 1 << 31 ),
57- AHCI_CMD_ATAPI = ( 1 << 5 ),
58- AHCI_CMD_WRITE = ( 1 << 6 ),
59- AHCI_CMD_PREFETCH = ( 1 << 7 ),
60- AHCI_CMD_RESET = ( 1 << 8 ),
61- AHCI_CMD_CLR_BUSY = ( 1 << 10 ),
57+ AHCI_IRQ_ON_SG = BIT ( 31 ),
58+ AHCI_CMD_ATAPI = BIT ( 5 ),
59+ AHCI_CMD_WRITE = BIT ( 6 ),
60+ AHCI_CMD_PREFETCH = BIT ( 7 ),
61+ AHCI_CMD_RESET = BIT ( 8 ),
62+ AHCI_CMD_CLR_BUSY = BIT ( 10 ),
6263
6364 RX_FIS_PIO_SETUP = 0x20 , /* offset of PIO Setup FIS data */
6465 RX_FIS_D2H_REG = 0x40 , /* offset of D2H Register FIS data */
@@ -76,37 +77,37 @@ enum {
7677 HOST_CAP2 = 0x24 , /* host capabilities, extended */
7778
7879 /* HOST_CTL bits */
79- HOST_RESET = ( 1 << 0 ), /* reset controller; self-clear */
80- HOST_IRQ_EN = ( 1 << 1 ), /* global IRQ enable */
81- HOST_MRSM = ( 1 << 2 ), /* MSI Revert to Single Message */
82- HOST_AHCI_EN = ( 1 << 31 ), /* AHCI enabled */
80+ HOST_RESET = BIT ( 0 ), /* reset controller; self-clear */
81+ HOST_IRQ_EN = BIT ( 1 ), /* global IRQ enable */
82+ HOST_MRSM = BIT ( 2 ), /* MSI Revert to Single Message */
83+ HOST_AHCI_EN = BIT ( 31 ), /* AHCI enabled */
8384
8485 /* HOST_CAP bits */
85- HOST_CAP_SXS = ( 1 << 5 ), /* Supports External SATA */
86- HOST_CAP_EMS = ( 1 << 6 ), /* Enclosure Management support */
87- HOST_CAP_CCC = ( 1 << 7 ), /* Command Completion Coalescing */
88- HOST_CAP_PART = ( 1 << 13 ), /* Partial state capable */
89- HOST_CAP_SSC = ( 1 << 14 ), /* Slumber state capable */
90- HOST_CAP_PIO_MULTI = ( 1 << 15 ), /* PIO multiple DRQ support */
91- HOST_CAP_FBS = ( 1 << 16 ), /* FIS-based switching support */
92- HOST_CAP_PMP = ( 1 << 17 ), /* Port Multiplier support */
93- HOST_CAP_ONLY = ( 1 << 18 ), /* Supports AHCI mode only */
94- HOST_CAP_CLO = ( 1 << 24 ), /* Command List Override support */
95- HOST_CAP_LED = ( 1 << 25 ), /* Supports activity LED */
96- HOST_CAP_ALPM = ( 1 << 26 ), /* Aggressive Link PM support */
97- HOST_CAP_SSS = ( 1 << 27 ), /* Staggered Spin-up */
98- HOST_CAP_MPS = ( 1 << 28 ), /* Mechanical presence switch */
99- HOST_CAP_SNTF = ( 1 << 29 ), /* SNotification register */
100- HOST_CAP_NCQ = ( 1 << 30 ), /* Native Command Queueing */
101- HOST_CAP_64 = ( 1 << 31 ), /* PCI DAC (64-bit DMA) support */
86+ HOST_CAP_SXS = BIT ( 5 ), /* Supports External SATA */
87+ HOST_CAP_EMS = BIT ( 6 ), /* Enclosure Management support */
88+ HOST_CAP_CCC = BIT ( 7 ), /* Command Completion Coalescing */
89+ HOST_CAP_PART = BIT ( 13 ), /* Partial state capable */
90+ HOST_CAP_SSC = BIT ( 14 ), /* Slumber state capable */
91+ HOST_CAP_PIO_MULTI = BIT ( 15 ), /* PIO multiple DRQ support */
92+ HOST_CAP_FBS = BIT ( 16 ), /* FIS-based switching support */
93+ HOST_CAP_PMP = BIT ( 17 ), /* Port Multiplier support */
94+ HOST_CAP_ONLY = BIT ( 18 ), /* Supports AHCI mode only */
95+ HOST_CAP_CLO = BIT ( 24 ), /* Command List Override support */
96+ HOST_CAP_LED = BIT ( 25 ), /* Supports activity LED */
97+ HOST_CAP_ALPM = BIT ( 26 ), /* Aggressive Link PM support */
98+ HOST_CAP_SSS = BIT ( 27 ), /* Staggered Spin-up */
99+ HOST_CAP_MPS = BIT ( 28 ), /* Mechanical presence switch */
100+ HOST_CAP_SNTF = BIT ( 29 ), /* SNotification register */
101+ HOST_CAP_NCQ = BIT ( 30 ), /* Native Command Queueing */
102+ HOST_CAP_64 = BIT ( 31 ), /* PCI DAC (64-bit DMA) support */
102103
103104 /* HOST_CAP2 bits */
104- HOST_CAP2_BOH = ( 1 << 0 ), /* BIOS/OS handoff supported */
105- HOST_CAP2_NVMHCI = ( 1 << 1 ), /* NVMHCI supported */
106- HOST_CAP2_APST = ( 1 << 2 ), /* Automatic partial to slumber */
107- HOST_CAP2_SDS = ( 1 << 3 ), /* Support device sleep */
108- HOST_CAP2_SADM = ( 1 << 4 ), /* Support aggressive DevSlp */
109- HOST_CAP2_DESO = ( 1 << 5 ), /* DevSlp from slumber only */
105+ HOST_CAP2_BOH = BIT ( 0 ), /* BIOS/OS handoff supported */
106+ HOST_CAP2_NVMHCI = BIT ( 1 ), /* NVMHCI supported */
107+ HOST_CAP2_APST = BIT ( 2 ), /* Automatic partial to slumber */
108+ HOST_CAP2_SDS = BIT ( 3 ), /* Support device sleep */
109+ HOST_CAP2_SADM = BIT ( 4 ), /* Support aggressive DevSlp */
110+ HOST_CAP2_DESO = BIT ( 5 ), /* DevSlp from slumber only */
110111
111112 /* registers for each SATA port */
112113 PORT_LST_ADDR = 0x00 , /* command list DMA addr */
@@ -128,24 +129,24 @@ enum {
128129 PORT_DEVSLP = 0x44 , /* device sleep */
129130
130131 /* PORT_IRQ_{STAT,MASK} bits */
131- PORT_IRQ_COLD_PRES = ( 1 << 31 ), /* cold presence detect */
132- PORT_IRQ_TF_ERR = ( 1 << 30 ), /* task file error */
133- PORT_IRQ_HBUS_ERR = ( 1 << 29 ), /* host bus fatal error */
134- PORT_IRQ_HBUS_DATA_ERR = ( 1 << 28 ), /* host bus data error */
135- PORT_IRQ_IF_ERR = ( 1 << 27 ), /* interface fatal error */
136- PORT_IRQ_IF_NONFATAL = ( 1 << 26 ), /* interface non-fatal error */
137- PORT_IRQ_OVERFLOW = ( 1 << 24 ), /* xfer exhausted available S/G */
138- PORT_IRQ_BAD_PMP = ( 1 << 23 ), /* incorrect port multiplier */
139-
140- PORT_IRQ_PHYRDY = ( 1 << 22 ), /* PhyRdy changed */
141- PORT_IRQ_DMPS = ( 1 << 7 ), /* mechanical presence status */
142- PORT_IRQ_CONNECT = ( 1 << 6 ), /* port connect change status */
143- PORT_IRQ_SG_DONE = ( 1 << 5 ), /* descriptor processed */
144- PORT_IRQ_UNK_FIS = ( 1 << 4 ), /* unknown FIS rx'd */
145- PORT_IRQ_SDB_FIS = ( 1 << 3 ), /* Set Device Bits FIS rx'd */
146- PORT_IRQ_DMAS_FIS = ( 1 << 2 ), /* DMA Setup FIS rx'd */
147- PORT_IRQ_PIOS_FIS = ( 1 << 1 ), /* PIO Setup FIS rx'd */
148- PORT_IRQ_D2H_REG_FIS = ( 1 << 0 ), /* D2H Register FIS rx'd */
132+ PORT_IRQ_COLD_PRES = BIT ( 31 ), /* cold presence detect */
133+ PORT_IRQ_TF_ERR = BIT ( 30 ), /* task file error */
134+ PORT_IRQ_HBUS_ERR = BIT ( 29 ), /* host bus fatal error */
135+ PORT_IRQ_HBUS_DATA_ERR = BIT ( 28 ), /* host bus data error */
136+ PORT_IRQ_IF_ERR = BIT ( 27 ), /* interface fatal error */
137+ PORT_IRQ_IF_NONFATAL = BIT ( 26 ), /* interface non-fatal error */
138+ PORT_IRQ_OVERFLOW = BIT ( 24 ), /* xfer exhausted available S/G */
139+ PORT_IRQ_BAD_PMP = BIT ( 23 ), /* incorrect port multiplier */
140+
141+ PORT_IRQ_PHYRDY = BIT ( 22 ), /* PhyRdy changed */
142+ PORT_IRQ_DMPS = BIT ( 7 ), /* mechanical presence status */
143+ PORT_IRQ_CONNECT = BIT ( 6 ), /* port connect change status */
144+ PORT_IRQ_SG_DONE = BIT ( 5 ), /* descriptor processed */
145+ PORT_IRQ_UNK_FIS = BIT ( 4 ), /* unknown FIS rx'd */
146+ PORT_IRQ_SDB_FIS = BIT ( 3 ), /* Set Device Bits FIS rx'd */
147+ PORT_IRQ_DMAS_FIS = BIT ( 2 ), /* DMA Setup FIS rx'd */
148+ PORT_IRQ_PIOS_FIS = BIT ( 1 ), /* PIO Setup FIS rx'd */
149+ PORT_IRQ_D2H_REG_FIS = BIT ( 0 ), /* D2H Register FIS rx'd */
149150
150151 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
151152 PORT_IRQ_IF_ERR |
@@ -161,27 +162,27 @@ enum {
161162 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS ,
162163
163164 /* PORT_CMD bits */
164- PORT_CMD_ASP = ( 1 << 27 ), /* Aggressive Slumber/Partial */
165- PORT_CMD_ALPE = ( 1 << 26 ), /* Aggressive Link PM enable */
166- PORT_CMD_ATAPI = ( 1 << 24 ), /* Device is ATAPI */
167- PORT_CMD_FBSCP = ( 1 << 22 ), /* FBS Capable Port */
168- PORT_CMD_ESP = ( 1 << 21 ), /* External Sata Port */
169- PORT_CMD_CPD = ( 1 << 20 ), /* Cold Presence Detection */
170- PORT_CMD_MPSP = ( 1 << 19 ), /* Mechanical Presence Switch */
171- PORT_CMD_HPCP = ( 1 << 18 ), /* HotPlug Capable Port */
172- PORT_CMD_PMP = ( 1 << 17 ), /* PMP attached */
173- PORT_CMD_LIST_ON = ( 1 << 15 ), /* cmd list DMA engine running */
174- PORT_CMD_FIS_ON = ( 1 << 14 ), /* FIS DMA engine running */
175- PORT_CMD_FIS_RX = ( 1 << 4 ), /* Enable FIS receive DMA engine */
176- PORT_CMD_CLO = ( 1 << 3 ), /* Command list override */
177- PORT_CMD_POWER_ON = ( 1 << 2 ), /* Power up device */
178- PORT_CMD_SPIN_UP = ( 1 << 1 ), /* Spin up device */
179- PORT_CMD_START = ( 1 << 0 ), /* Enable port DMA engine */
180-
181- PORT_CMD_ICC_MASK = (0xf << 28 ), /* i/f ICC state mask */
182- PORT_CMD_ICC_ACTIVE = (0x1 << 28 ), /* Put i/f in active state */
183- PORT_CMD_ICC_PARTIAL = (0x2 << 28 ), /* Put i/f in partial state */
184- PORT_CMD_ICC_SLUMBER = (0x6 << 28 ), /* Put i/f in slumber state */
165+ PORT_CMD_ASP = BIT ( 27 ), /* Aggressive Slumber/Partial */
166+ PORT_CMD_ALPE = BIT ( 26 ), /* Aggressive Link PM enable */
167+ PORT_CMD_ATAPI = BIT ( 24 ), /* Device is ATAPI */
168+ PORT_CMD_FBSCP = BIT ( 22 ), /* FBS Capable Port */
169+ PORT_CMD_ESP = BIT ( 21 ), /* External Sata Port */
170+ PORT_CMD_CPD = BIT ( 20 ), /* Cold Presence Detection */
171+ PORT_CMD_MPSP = BIT ( 19 ), /* Mechanical Presence Switch */
172+ PORT_CMD_HPCP = BIT ( 18 ), /* HotPlug Capable Port */
173+ PORT_CMD_PMP = BIT ( 17 ), /* PMP attached */
174+ PORT_CMD_LIST_ON = BIT ( 15 ), /* cmd list DMA engine running */
175+ PORT_CMD_FIS_ON = BIT ( 14 ), /* FIS DMA engine running */
176+ PORT_CMD_FIS_RX = BIT ( 4 ), /* Enable FIS receive DMA engine */
177+ PORT_CMD_CLO = BIT ( 3 ), /* Command list override */
178+ PORT_CMD_POWER_ON = BIT ( 2 ), /* Power up device */
179+ PORT_CMD_SPIN_UP = BIT ( 1 ), /* Spin up device */
180+ PORT_CMD_START = BIT ( 0 ), /* Enable port DMA engine */
181+
182+ PORT_CMD_ICC_MASK = (0xfu << 28 ), /* i/f ICC state mask */
183+ PORT_CMD_ICC_ACTIVE = (0x1u << 28 ), /* Put i/f in active state */
184+ PORT_CMD_ICC_PARTIAL = (0x2u << 28 ), /* Put i/f in partial state */
185+ PORT_CMD_ICC_SLUMBER = (0x6u << 28 ), /* Put i/f in slumber state */
185186
186187 /* PORT_CMD capabilities mask */
187188 PORT_CMD_CAP = PORT_CMD_HPCP | PORT_CMD_MPSP |
@@ -192,60 +193,60 @@ enum {
192193 PORT_FBS_ADO_OFFSET = 12 , /* FBS active dev optimization offset */
193194 PORT_FBS_DEV_OFFSET = 8 , /* FBS device to issue offset */
194195 PORT_FBS_DEV_MASK = (0xf << PORT_FBS_DEV_OFFSET ), /* FBS.DEV */
195- PORT_FBS_SDE = ( 1 << 2 ), /* FBS single device error */
196- PORT_FBS_DEC = ( 1 << 1 ), /* FBS device error clear */
197- PORT_FBS_EN = ( 1 << 0 ), /* Enable FBS */
196+ PORT_FBS_SDE = BIT ( 2 ), /* FBS single device error */
197+ PORT_FBS_DEC = BIT ( 1 ), /* FBS device error clear */
198+ PORT_FBS_EN = BIT ( 0 ), /* Enable FBS */
198199
199200 /* PORT_DEVSLP bits */
200201 PORT_DEVSLP_DM_OFFSET = 25 , /* DITO multiplier offset */
201202 PORT_DEVSLP_DM_MASK = (0xf << 25 ), /* DITO multiplier mask */
202203 PORT_DEVSLP_DITO_OFFSET = 15 , /* DITO offset */
203204 PORT_DEVSLP_MDAT_OFFSET = 10 , /* Minimum assertion time */
204205 PORT_DEVSLP_DETO_OFFSET = 2 , /* DevSlp exit timeout */
205- PORT_DEVSLP_DSP = ( 1 << 1 ), /* DevSlp present */
206- PORT_DEVSLP_ADSE = ( 1 << 0 ), /* Aggressive DevSlp enable */
206+ PORT_DEVSLP_DSP = BIT ( 1 ), /* DevSlp present */
207+ PORT_DEVSLP_ADSE = BIT ( 0 ), /* Aggressive DevSlp enable */
207208
208209 /* hpriv->flags bits */
209210
210211#define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
211212
212- AHCI_HFLAG_NO_NCQ = ( 1 << 0 ),
213- AHCI_HFLAG_IGN_IRQ_IF_ERR = ( 1 << 1 ), /* ignore IRQ_IF_ERR */
214- AHCI_HFLAG_IGN_SERR_INTERNAL = ( 1 << 2 ), /* ignore SERR_INTERNAL */
215- AHCI_HFLAG_32BIT_ONLY = ( 1 << 3 ), /* force 32bit */
216- AHCI_HFLAG_MV_PATA = ( 1 << 4 ), /* PATA port */
217- AHCI_HFLAG_NO_MSI = ( 1 << 5 ), /* no PCI MSI */
218- AHCI_HFLAG_NO_PMP = ( 1 << 6 ), /* no PMP */
219- AHCI_HFLAG_SECT255 = ( 1 << 8 ), /* max 255 sectors */
220- AHCI_HFLAG_YES_NCQ = ( 1 << 9 ), /* force NCQ cap on */
221- AHCI_HFLAG_NO_SUSPEND = ( 1 << 10 ), /* don't suspend */
222- AHCI_HFLAG_SRST_TOUT_IS_OFFLINE = ( 1 << 11 ), /* treat SRST timeout as
223- link offline */
224- AHCI_HFLAG_NO_SNTF = ( 1 << 12 ), /* no sntf */
225- AHCI_HFLAG_NO_FPDMA_AA = ( 1 << 13 ), /* no FPDMA AA */
226- AHCI_HFLAG_YES_FBS = ( 1 << 14 ), /* force FBS cap on */
227- AHCI_HFLAG_DELAY_ENGINE = ( 1 << 15 ), /* do not start engine on
228- port start (wait until
229- error-handling stage) */
230- AHCI_HFLAG_NO_DEVSLP = ( 1 << 17 ), /* no device sleep */
231- AHCI_HFLAG_NO_FBS = ( 1 << 18 ), /* no FBS */
213+ AHCI_HFLAG_NO_NCQ = BIT ( 0 ),
214+ AHCI_HFLAG_IGN_IRQ_IF_ERR = BIT ( 1 ), /* ignore IRQ_IF_ERR */
215+ AHCI_HFLAG_IGN_SERR_INTERNAL = BIT ( 2 ), /* ignore SERR_INTERNAL */
216+ AHCI_HFLAG_32BIT_ONLY = BIT ( 3 ), /* force 32bit */
217+ AHCI_HFLAG_MV_PATA = BIT ( 4 ), /* PATA port */
218+ AHCI_HFLAG_NO_MSI = BIT ( 5 ), /* no PCI MSI */
219+ AHCI_HFLAG_NO_PMP = BIT ( 6 ), /* no PMP */
220+ AHCI_HFLAG_SECT255 = BIT ( 8 ), /* max 255 sectors */
221+ AHCI_HFLAG_YES_NCQ = BIT ( 9 ), /* force NCQ cap on */
222+ AHCI_HFLAG_NO_SUSPEND = BIT ( 10 ), /* don't suspend */
223+ AHCI_HFLAG_SRST_TOUT_IS_OFFLINE = BIT ( 11 ), /* treat SRST timeout as
224+ link offline */
225+ AHCI_HFLAG_NO_SNTF = BIT ( 12 ), /* no sntf */
226+ AHCI_HFLAG_NO_FPDMA_AA = BIT ( 13 ), /* no FPDMA AA */
227+ AHCI_HFLAG_YES_FBS = BIT ( 14 ), /* force FBS cap on */
228+ AHCI_HFLAG_DELAY_ENGINE = BIT ( 15 ), /* do not start engine on
229+ port start (wait until
230+ error-handling stage) */
231+ AHCI_HFLAG_NO_DEVSLP = BIT ( 17 ), /* no device sleep */
232+ AHCI_HFLAG_NO_FBS = BIT ( 18 ), /* no FBS */
232233
233234#ifdef CONFIG_PCI_MSI
234- AHCI_HFLAG_MULTI_MSI = ( 1 << 20 ), /* per-port MSI(-X) */
235+ AHCI_HFLAG_MULTI_MSI = BIT ( 20 ), /* per-port MSI(-X) */
235236#else
236237 /* compile out MSI infrastructure */
237238 AHCI_HFLAG_MULTI_MSI = 0 ,
238239#endif
239- AHCI_HFLAG_WAKE_BEFORE_STOP = ( 1 << 22 ), /* wake before DMA stop */
240- AHCI_HFLAG_YES_ALPM = ( 1 << 23 ), /* force ALPM cap on */
241- AHCI_HFLAG_NO_WRITE_TO_RO = ( 1 << 24 ), /* don't write to read
242- only registers */
243- AHCI_HFLAG_USE_LPM_POLICY = ( 1 << 25 ), /* chipset that should use
244- SATA_MOBILE_LPM_POLICY
245- as default lpm_policy */
246- AHCI_HFLAG_SUSPEND_PHYS = ( 1 << 26 ), /* handle PHYs during
247- suspend/resume */
248- AHCI_HFLAG_NO_SXS = ( 1 << 28 ), /* SXS not supported */
240+ AHCI_HFLAG_WAKE_BEFORE_STOP = BIT ( 22 ), /* wake before DMA stop */
241+ AHCI_HFLAG_YES_ALPM = BIT ( 23 ), /* force ALPM cap on */
242+ AHCI_HFLAG_NO_WRITE_TO_RO = BIT ( 24 ), /* don't write to read
243+ only registers */
244+ AHCI_HFLAG_USE_LPM_POLICY = BIT ( 25 ), /* chipset that should use
245+ SATA_MOBILE_LPM_POLICY
246+ as default lpm_policy */
247+ AHCI_HFLAG_SUSPEND_PHYS = BIT ( 26 ), /* handle PHYs during
248+ suspend/resume */
249+ AHCI_HFLAG_NO_SXS = BIT ( 28 ), /* SXS not supported */
249250
250251 /* ap->flags bits */
251252
@@ -261,22 +262,22 @@ enum {
261262 EM_MAX_RETRY = 5 ,
262263
263264 /* em_ctl bits */
264- EM_CTL_RST = ( 1 << 9 ), /* Reset */
265- EM_CTL_TM = ( 1 << 8 ), /* Transmit Message */
266- EM_CTL_MR = ( 1 << 0 ), /* Message Received */
267- EM_CTL_ALHD = ( 1 << 26 ), /* Activity LED */
268- EM_CTL_XMT = ( 1 << 25 ), /* Transmit Only */
269- EM_CTL_SMB = ( 1 << 24 ), /* Single Message Buffer */
270- EM_CTL_SGPIO = ( 1 << 19 ), /* SGPIO messages supported */
271- EM_CTL_SES = ( 1 << 18 ), /* SES-2 messages supported */
272- EM_CTL_SAFTE = ( 1 << 17 ), /* SAF-TE messages supported */
273- EM_CTL_LED = ( 1 << 16 ), /* LED messages supported */
265+ EM_CTL_RST = BIT ( 9 ), /* Reset */
266+ EM_CTL_TM = BIT ( 8 ), /* Transmit Message */
267+ EM_CTL_MR = BIT ( 0 ), /* Message Received */
268+ EM_CTL_ALHD = BIT ( 26 ), /* Activity LED */
269+ EM_CTL_XMT = BIT ( 25 ), /* Transmit Only */
270+ EM_CTL_SMB = BIT ( 24 ), /* Single Message Buffer */
271+ EM_CTL_SGPIO = BIT ( 19 ), /* SGPIO messages supported */
272+ EM_CTL_SES = BIT ( 18 ), /* SES-2 messages supported */
273+ EM_CTL_SAFTE = BIT ( 17 ), /* SAF-TE messages supported */
274+ EM_CTL_LED = BIT ( 16 ), /* LED messages supported */
274275
275276 /* em message type */
276- EM_MSG_TYPE_LED = ( 1 << 0 ), /* LED */
277- EM_MSG_TYPE_SAFTE = ( 1 << 1 ), /* SAF-TE */
278- EM_MSG_TYPE_SES2 = ( 1 << 2 ), /* SES-2 */
279- EM_MSG_TYPE_SGPIO = ( 1 << 3 ), /* SGPIO */
277+ EM_MSG_TYPE_LED = BIT ( 0 ), /* LED */
278+ EM_MSG_TYPE_SAFTE = BIT ( 1 ), /* SAF-TE */
279+ EM_MSG_TYPE_SES2 = BIT ( 2 ), /* SES-2 */
280+ EM_MSG_TYPE_SGPIO = BIT ( 3 ), /* SGPIO */
280281};
281282
282283struct ahci_cmd_hdr {
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