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perf vendor events intel: Refresh ivytown metrics and events
Update the ivytown metrics and events using the new tooling from: https://github.com/intel/perfmon The metrics are unchanged but the formulas differ due to parentheses, use of exponents and removal of redundant operations like "* 1". The events are unchanged but unused json values are removed. The formatting changes increase consistency across the json files. Signed-off-by: Ian Rogers <[email protected]> Acked-by: Kan Liang <[email protected]> Cc: Adrian Hunter <[email protected]> Cc: Alexander Shishkin <[email protected]> Cc: Caleb Biggers <[email protected]> Cc: Ingo Molnar <[email protected]> Cc: Jiri Olsa <[email protected]> Cc: John Garry <[email protected]> Cc: Mark Rutland <[email protected]> Cc: Namhyung Kim <[email protected]> Cc: Perry Taylor <[email protected]> Cc: Peter Zijlstra <[email protected]> Cc: Stephane Eranian <[email protected]> Cc: Xing Zhengjun <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Arnaldo Carvalho de Melo <[email protected]>
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‎tools/perf/pmu-events/arch/x86/ivytown/cache.json

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‎tools/perf/pmu-events/arch/x86/ivytown/floating-point.json

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@@ -1,8 +1,6 @@
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[
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{
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"BriefDescription": "Cycles with any input/output SSE or FP assist",
4-
"Counter": "0,1,2,3",
5-
"CounterHTOff": "0,1,2,3",
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"CounterMask": "1",
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"EventCode": "0xCA",
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"EventName": "FP_ASSIST.ANY",
@@ -12,8 +10,6 @@
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},
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{
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"BriefDescription": "Number of SIMD FP assists due to input values",
15-
"Counter": "0,1,2,3",
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"CounterHTOff": "0,1,2,3,4,5,6,7",
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"EventCode": "0xCA",
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"EventName": "FP_ASSIST.SIMD_INPUT",
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"PublicDescription": "Number of SIMD FP assists due to input values.",
@@ -22,8 +18,6 @@
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},
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{
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"BriefDescription": "Number of SIMD FP assists due to Output values",
25-
"Counter": "0,1,2,3",
26-
"CounterHTOff": "0,1,2,3,4,5,6,7",
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"EventCode": "0xCA",
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"EventName": "FP_ASSIST.SIMD_OUTPUT",
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"PublicDescription": "Number of SIMD FP assists due to output values.",
@@ -32,8 +26,6 @@
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},
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{
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"BriefDescription": "Number of X87 assists due to input value.",
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"Counter": "0,1,2,3",
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"CounterHTOff": "0,1,2,3,4,5,6,7",
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"EventCode": "0xCA",
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"EventName": "FP_ASSIST.X87_INPUT",
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"PublicDescription": "Number of X87 FP assists due to input values.",
@@ -42,8 +34,6 @@
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},
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{
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"BriefDescription": "Number of X87 assists due to output value.",
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"Counter": "0,1,2,3",
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"CounterHTOff": "0,1,2,3,4,5,6,7",
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"EventCode": "0xCA",
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"EventName": "FP_ASSIST.X87_OUTPUT",
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"PublicDescription": "Number of X87 FP assists due to output values.",
@@ -52,8 +42,6 @@
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},
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{
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"BriefDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle",
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"Counter": "0,1,2,3",
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"CounterHTOff": "0,1,2,3,4,5,6,7",
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"EventCode": "0x10",
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"EventName": "FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE",
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"PublicDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle.",
@@ -62,8 +50,6 @@
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},
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{
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"BriefDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle",
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"Counter": "0,1,2,3",
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"CounterHTOff": "0,1,2,3,4,5,6,7",
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"EventCode": "0x10",
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"EventName": "FP_COMP_OPS_EXE.SSE_PACKED_SINGLE",
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"PublicDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle.",
@@ -72,8 +58,6 @@
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},
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{
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"BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar double-precision uops issued this cycle",
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"Counter": "0,1,2,3",
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"CounterHTOff": "0,1,2,3,4,5,6,7",
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"EventCode": "0x10",
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"EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE",
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"PublicDescription": "Counts number of SSE* or AVX-128 double precision FP scalar uops executed.",
@@ -82,8 +66,6 @@
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},
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{
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"BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle",
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"Counter": "0,1,2,3",
86-
"CounterHTOff": "0,1,2,3,4,5,6,7",
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"EventCode": "0x10",
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"EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE",
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"PublicDescription": "Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle.",
@@ -92,8 +74,6 @@
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},
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{
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"BriefDescription": "Number of FP Computational Uops Executed this cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULs and IMULs, FDIVs, FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish an FADD used in the middle of a transcendental flow from a s",
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"Counter": "0,1,2,3",
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"CounterHTOff": "0,1,2,3,4,5,6,7",
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"EventCode": "0x10",
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"EventName": "FP_COMP_OPS_EXE.X87",
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"PublicDescription": "Counts number of X87 uops executed.",
@@ -102,26 +82,20 @@
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},
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{
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"BriefDescription": "Number of SIMD Move Elimination candidate uops that were eliminated.",
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"Counter": "0,1,2,3",
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"CounterHTOff": "0,1,2,3,4,5,6,7",
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"EventCode": "0x58",
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"EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED",
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"SampleAfterValue": "1000003",
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"UMask": "0x2"
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},
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{
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"BriefDescription": "Number of SIMD Move Elimination candidate uops that were not eliminated.",
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"Counter": "0,1,2,3",
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"CounterHTOff": "0,1,2,3,4,5,6,7",
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"EventCode": "0x58",
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"EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED",
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"SampleAfterValue": "1000003",
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"UMask": "0x8"
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},
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{
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"BriefDescription": "Number of GSSE memory assist for stores. GSSE microcode assist is being invoked whenever the hardware is unable to properly handle GSSE-256b operations.",
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"Counter": "0,1,2,3",
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"CounterHTOff": "0,1,2,3,4,5,6,7",
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"EventCode": "0xC1",
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"EventName": "OTHER_ASSISTS.AVX_STORE",
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"PublicDescription": "Number of assists associated with 256-bit AVX store operations.",
@@ -130,26 +104,20 @@
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},
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{
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"BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.",
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"Counter": "0,1,2,3",
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"CounterHTOff": "0,1,2,3,4,5,6,7",
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"EventCode": "0xC1",
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"EventName": "OTHER_ASSISTS.AVX_TO_SSE",
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"SampleAfterValue": "100003",
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"UMask": "0x10"
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},
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{
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"BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.",
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"Counter": "0,1,2,3",
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"CounterHTOff": "0,1,2,3,4,5,6,7",
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"EventCode": "0xC1",
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"EventName": "OTHER_ASSISTS.SSE_TO_AVX",
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"SampleAfterValue": "100003",
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"UMask": "0x20"
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},
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{
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"BriefDescription": "number of AVX-256 Computational FP double precision uops issued this cycle",
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"Counter": "0,1,2,3",
152-
"CounterHTOff": "0,1,2,3,4,5,6,7",
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"EventCode": "0x11",
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"EventName": "SIMD_FP_256.PACKED_DOUBLE",
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"PublicDescription": "Counts 256-bit packed double-precision floating-point instructions.",
@@ -158,8 +126,6 @@
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},
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{
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"BriefDescription": "number of GSSE-256 Computational FP single precision uops issued this cycle",
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"Counter": "0,1,2,3",
162-
"CounterHTOff": "0,1,2,3,4,5,6,7",
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"EventCode": "0x11",
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"EventName": "SIMD_FP_256.PACKED_SINGLE",
165131
"PublicDescription": "Counts 256-bit packed single-precision floating-point instructions.",

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