@@ -1384,7 +1384,7 @@ struct driver_data {
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};
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/*
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- * This function apppends a packet to the DMA queue for transmission.
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+ * This function appends a packet to the DMA queue for transmission.
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* Must always be called with the ochi->lock held to ensure proper
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* generation handling and locking around packet queue manipulation.
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*/
@@ -2213,7 +2213,7 @@ static irqreturn_t irq_handler(int irq, void *data)
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if (unlikely (param_debug > 0 )) {
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dev_notice_ratelimited (ohci -> card .device ,
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- "The debug parameter is superceded by tracepoints events, and deprecated." );
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+ "The debug parameter is superseded by tracepoints events, and deprecated." );
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}
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/*
@@ -2614,7 +2614,7 @@ static int ohci_set_config_rom(struct fw_card *card,
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* ConfigRomHeader and BusOptions doesn't honor the
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* noByteSwapData bit, so with a be32 config rom, the
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* controller will load be32 values in to these registers
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- * during the atomic update, even on litte endian
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+ * during the atomic update, even on little endian
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* architectures. The workaround we use is to put a 0 in the
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* header quadlet; 0 is endian agnostic and means that the
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* config rom isn't ready yet. In the bus reset tasklet we
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