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75 | 75 |
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76 | 76 | /* Vendor2 MMD registers */
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77 | 77 | MV_V2_PORT_CTRL = 0xf001,
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78 |
| - MV_V2_PORT_CTRL_PWRDOWN = 0x0800, |
| 78 | + MV_V2_PORT_CTRL_SWRST = BIT(15), |
| 79 | + MV_V2_PORT_CTRL_PWRDOWN = BIT(11), |
79 | 80 | MV_V2_TEMP_CTRL = 0xf08a,
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80 | 81 | MV_V2_TEMP_CTRL_MASK = 0xc000,
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81 | 82 | MV_V2_TEMP_CTRL_SAMPLE = 0x0000,
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@@ -239,8 +240,17 @@ static int mv3310_power_down(struct phy_device *phydev)
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239 | 240 |
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240 | 241 | static int mv3310_power_up(struct phy_device *phydev)
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241 | 242 | {
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242 |
| - return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL, |
243 |
| - MV_V2_PORT_CTRL_PWRDOWN); |
| 243 | + struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); |
| 244 | + int ret; |
| 245 | + |
| 246 | + ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL, |
| 247 | + MV_V2_PORT_CTRL_PWRDOWN); |
| 248 | + |
| 249 | + if (priv->firmware_ver < 0x00030000) |
| 250 | + return ret; |
| 251 | + |
| 252 | + return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL, |
| 253 | + MV_V2_PORT_CTRL_SWRST); |
244 | 254 | }
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245 | 255 |
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246 | 256 | static int mv3310_reset(struct phy_device *phydev, u32 unit)
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