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Commit 916fc60

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Merge tag 'pci-v6.3-fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci
Pull PCI fix from Bjorn Helgaas: - Fix DesignWare PORT_LINK_CONTROL setup, which was corrupted when the DT "snps,enable-cdm-check" property was present (Yoshihiro Shimoda) * tag 'pci-v6.3-fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci: PCI: dwc: Fix PORT_LINK_CONTROL update when CDM check enabled
2 parents 3df82e4 + cdce670 commit 916fc60

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drivers/pci/controller/dwc/pcie-designware.c

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1001,18 +1001,18 @@ void dw_pcie_setup(struct dw_pcie *pci)
10011001
dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
10021002
}
10031003

1004-
val = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL);
1005-
val &= ~PORT_LINK_FAST_LINK_MODE;
1006-
val |= PORT_LINK_DLL_LINK_EN;
1007-
dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val);
1008-
10091004
if (dw_pcie_cap_is(pci, CDM_CHECK)) {
10101005
val = dw_pcie_readl_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS);
10111006
val |= PCIE_PL_CHK_REG_CHK_REG_CONTINUOUS |
10121007
PCIE_PL_CHK_REG_CHK_REG_START;
10131008
dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, val);
10141009
}
10151010

1011+
val = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL);
1012+
val &= ~PORT_LINK_FAST_LINK_MODE;
1013+
val |= PORT_LINK_DLL_LINK_EN;
1014+
dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val);
1015+
10161016
if (!pci->num_lanes) {
10171017
dev_dbg(pci->dev, "Using h/w default number of lanes\n");
10181018
return;

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