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bjorn-helgaasbjorn-helgaas
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Merge branch 'pci/ctrl/qcom'
- Add PHY clock source implementation (Dmitry Baryshkov) - Use new clk_regmap_phy_mux_ops for gcc-sm8450 and gcc-sc7280 PCIe pipe clocks (Dmitry Baryshkov) - Set up rev 2.1.0 PARF_PHY before enabling clocks (Christian Marangi) - Power on PHY before accessing IPQ8074 DBI registers to avoid boot hangs (Robert Marko) - Power on PHY before accessing DBI registers on all variants for consistency (Robert Marko) - Remove unnecessary pipe_clk handling since this is done in PHY drivers (Dmitry Baryshkov) - Drop manual pipe_clk_src handling (Dmitry Baryshkov) - Move GEN3_RELATED DBI definitions to common dwc header (Baruch Siach) - Define slot capabilities using generic PCI_EXP_SLTCAP_* macros (Baruch Siach) - Add IPQ60xx support (Selvam Sathappan Periakaruppan) - Fix DT description typo (Baruch Siach) - Fix DT "compatibles" typo (Johan Hovold) - Allow ASPM L1 and substates for 2.7.0 (Krishna chaitanya chundru) * pci/ctrl/qcom: PCI: qcom: Allow ASPM L1 and substates for 2.7.0 dt-bindings: PCI: qcom: Fix reset conditional dt-bindings: PCI: qcom: Fix description typo PCI: qcom: Add IPQ60xx support PCI: qcom: Define slot capabilities using PCI_EXP_SLTCAP_* PCI: dwc: Move GEN3_RELATED DBI definitions to common header PCI: qcom: Drop manual pipe_clk_src handling PCI: qcom: Remove unnecessary pipe_clk handling PCI: qcom: Power on PHY before DBI register accesses PCI: qcom: Power on PHY before IPQ8074 DBI register accesses PCI: qcom: Set up rev 2.1.0 PARF_PHY before enabling clocks clk: qcom: gcc-sc7280: use new clk_regmap_phy_mux_ops for PCIe pipe clocks clk: qcom: gcc-sm8450: use new clk_regmap_phy_mux_ops for PCIe pipe clocks clk: qcom: regmap: add PHY clock source implementation
2 parents 4faef10 + 5147ba8 commit 9195e6d

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+402
-236
lines changed

9 files changed

+402
-236
lines changed

‎Documentation/devicetree/bindings/pci/qcom,pcie.yaml

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -11,7 +11,7 @@ maintainers:
1111
- Stanimir Varbanov <[email protected]>
1212

1313
description: |
14-
Qualcomm PCIe root complex controller is bansed on the Synopsys DesignWare
14+
Qualcomm PCIe root complex controller is based on the Synopsys DesignWare
1515
PCIe IP.
1616
1717
properties:
@@ -615,7 +615,7 @@ allOf:
615615
- if:
616616
not:
617617
properties:
618-
compatibles:
618+
compatible:
619619
contains:
620620
enum:
621621
- qcom,pcie-msm8996

‎drivers/clk/qcom/Makefile

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -11,6 +11,7 @@ clk-qcom-y += clk-branch.o
1111
clk-qcom-y += clk-regmap-divider.o
1212
clk-qcom-y += clk-regmap-mux.o
1313
clk-qcom-y += clk-regmap-mux-div.o
14+
clk-qcom-y += clk-regmap-phy-mux.o
1415
clk-qcom-$(CONFIG_KRAIT_CLOCKS) += clk-krait.o
1516
clk-qcom-y += clk-hfpll.o
1617
clk-qcom-y += reset.o

‎drivers/clk/qcom/clk-regmap-phy-mux.c

Lines changed: 62 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,62 @@
1+
// SPDX-License-Identifier: GPL-2.0-only
2+
/*
3+
* Copyright (c) 2022, Linaro Ltd.
4+
*/
5+
6+
#include <linux/clk-provider.h>
7+
#include <linux/bitfield.h>
8+
#include <linux/regmap.h>
9+
#include <linux/export.h>
10+
11+
#include "clk-regmap.h"
12+
#include "clk-regmap-phy-mux.h"
13+
14+
#define PHY_MUX_MASK GENMASK(1, 0)
15+
#define PHY_MUX_PHY_SRC 0
16+
#define PHY_MUX_REF_SRC 2
17+
18+
static inline struct clk_regmap_phy_mux *to_clk_regmap_phy_mux(struct clk_regmap *clkr)
19+
{
20+
return container_of(clkr, struct clk_regmap_phy_mux, clkr);
21+
}
22+
23+
static int phy_mux_is_enabled(struct clk_hw *hw)
24+
{
25+
struct clk_regmap *clkr = to_clk_regmap(hw);
26+
struct clk_regmap_phy_mux *phy_mux = to_clk_regmap_phy_mux(clkr);
27+
unsigned int val;
28+
29+
regmap_read(clkr->regmap, phy_mux->reg, &val);
30+
val = FIELD_GET(PHY_MUX_MASK, val);
31+
32+
WARN_ON(val != PHY_MUX_PHY_SRC && val != PHY_MUX_REF_SRC);
33+
34+
return val == PHY_MUX_PHY_SRC;
35+
}
36+
37+
static int phy_mux_enable(struct clk_hw *hw)
38+
{
39+
struct clk_regmap *clkr = to_clk_regmap(hw);
40+
struct clk_regmap_phy_mux *phy_mux = to_clk_regmap_phy_mux(clkr);
41+
42+
return regmap_update_bits(clkr->regmap, phy_mux->reg,
43+
PHY_MUX_MASK,
44+
FIELD_PREP(PHY_MUX_MASK, PHY_MUX_PHY_SRC));
45+
}
46+
47+
static void phy_mux_disable(struct clk_hw *hw)
48+
{
49+
struct clk_regmap *clkr = to_clk_regmap(hw);
50+
struct clk_regmap_phy_mux *phy_mux = to_clk_regmap_phy_mux(clkr);
51+
52+
regmap_update_bits(clkr->regmap, phy_mux->reg,
53+
PHY_MUX_MASK,
54+
FIELD_PREP(PHY_MUX_MASK, PHY_MUX_REF_SRC));
55+
}
56+
57+
const struct clk_ops clk_regmap_phy_mux_ops = {
58+
.enable = phy_mux_enable,
59+
.disable = phy_mux_disable,
60+
.is_enabled = phy_mux_is_enabled,
61+
};
62+
EXPORT_SYMBOL_GPL(clk_regmap_phy_mux_ops);

‎drivers/clk/qcom/clk-regmap-phy-mux.h

Lines changed: 33 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,33 @@
1+
/* SPDX-License-Identifier: GPL-2.0-only */
2+
/*
3+
* Copyright (c) 2022, Linaro Ltd.
4+
*/
5+
6+
#ifndef __QCOM_CLK_REGMAP_PHY_MUX_H__
7+
#define __QCOM_CLK_REGMAP_PHY_MUX_H__
8+
9+
#include "clk-regmap.h"
10+
11+
/*
12+
* A clock implementation for PHY pipe and symbols clock muxes.
13+
*
14+
* If the clock is running off the from-PHY source, report it as enabled.
15+
* Report it as disabled otherwise (if it uses reference source).
16+
*
17+
* This way the PHY will disable the pipe clock before turning off the GDSC,
18+
* which in turn would lead to disabling corresponding pipe_clk_src (and thus
19+
* it being parked to a safe, reference clock source). And vice versa, after
20+
* enabling the GDSC the PHY will enable the pipe clock, which would cause
21+
* pipe_clk_src to be switched from a safe source to the working one.
22+
*
23+
* For some platforms this should be used for the UFS symbol_clk_src clocks
24+
* too.
25+
*/
26+
struct clk_regmap_phy_mux {
27+
u32 reg;
28+
struct clk_regmap clkr;
29+
};
30+
31+
extern const struct clk_ops clk_regmap_phy_mux_ops;
32+
33+
#endif

‎drivers/clk/qcom/gcc-sc7280.c

Lines changed: 15 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -17,6 +17,7 @@
1717
#include "clk-rcg.h"
1818
#include "clk-regmap-divider.h"
1919
#include "clk-regmap-mux.h"
20+
#include "clk-regmap-phy-mux.h"
2021
#include "common.h"
2122
#include "gdsc.h"
2223
#include "reset.h"
@@ -255,26 +256,6 @@ static const struct clk_parent_data gcc_parent_data_5[] = {
255256
{ .hw = &gcc_gpll0_out_even.clkr.hw },
256257
};
257258

258-
static const struct parent_map gcc_parent_map_6[] = {
259-
{ P_PCIE_0_PIPE_CLK, 0 },
260-
{ P_BI_TCXO, 2 },
261-
};
262-
263-
static const struct clk_parent_data gcc_parent_data_6[] = {
264-
{ .fw_name = "pcie_0_pipe_clk", .name = "pcie_0_pipe_clk" },
265-
{ .fw_name = "bi_tcxo" },
266-
};
267-
268-
static const struct parent_map gcc_parent_map_7[] = {
269-
{ P_PCIE_1_PIPE_CLK, 0 },
270-
{ P_BI_TCXO, 2 },
271-
};
272-
273-
static const struct clk_parent_data gcc_parent_data_7[] = {
274-
{ .fw_name = "pcie_1_pipe_clk", .name = "pcie_1_pipe_clk" },
275-
{ .fw_name = "bi_tcxo" },
276-
};
277-
278259
static const struct parent_map gcc_parent_map_8[] = {
279260
{ P_BI_TCXO, 0 },
280261
{ P_GCC_GPLL0_OUT_MAIN, 1 },
@@ -369,32 +350,32 @@ static const struct clk_parent_data gcc_parent_data_15[] = {
369350
{ .hw = &gcc_mss_gpll0_main_div_clk_src.clkr.hw },
370351
};
371352

372-
static struct clk_regmap_mux gcc_pcie_0_pipe_clk_src = {
353+
static struct clk_regmap_phy_mux gcc_pcie_0_pipe_clk_src = {
373354
.reg = 0x6b054,
374-
.shift = 0,
375-
.width = 2,
376-
.parent_map = gcc_parent_map_6,
377355
.clkr = {
378356
.hw.init = &(struct clk_init_data){
379357
.name = "gcc_pcie_0_pipe_clk_src",
380-
.parent_data = gcc_parent_data_6,
381-
.num_parents = ARRAY_SIZE(gcc_parent_data_6),
382-
.ops = &clk_regmap_mux_closest_ops,
358+
.parent_data = &(const struct clk_parent_data){
359+
.fw_name = "pcie_0_pipe_clk",
360+
.name = "pcie_0_pipe_clk",
361+
},
362+
.num_parents = 1,
363+
.ops = &clk_regmap_phy_mux_ops,
383364
},
384365
},
385366
};
386367

387-
static struct clk_regmap_mux gcc_pcie_1_pipe_clk_src = {
368+
static struct clk_regmap_phy_mux gcc_pcie_1_pipe_clk_src = {
388369
.reg = 0x8d054,
389-
.shift = 0,
390-
.width = 2,
391-
.parent_map = gcc_parent_map_7,
392370
.clkr = {
393371
.hw.init = &(struct clk_init_data){
394372
.name = "gcc_pcie_1_pipe_clk_src",
395-
.parent_data = gcc_parent_data_7,
396-
.num_parents = ARRAY_SIZE(gcc_parent_data_7),
397-
.ops = &clk_regmap_mux_closest_ops,
373+
.parent_data = &(const struct clk_parent_data){
374+
.fw_name = "pcie_1_pipe_clk",
375+
.name = "pcie_1_pipe_clk",
376+
},
377+
.num_parents = 1,
378+
.ops = &clk_regmap_phy_mux_ops,
398379
},
399380
},
400381
};

‎drivers/clk/qcom/gcc-sm8450.c

Lines changed: 13 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -17,6 +17,7 @@
1717
#include "clk-regmap.h"
1818
#include "clk-regmap-divider.h"
1919
#include "clk-regmap-mux.h"
20+
#include "clk-regmap-phy-mux.h"
2021
#include "gdsc.h"
2122
#include "reset.h"
2223

@@ -26,9 +27,7 @@ enum {
2627
P_GCC_GPLL0_OUT_MAIN,
2728
P_GCC_GPLL4_OUT_MAIN,
2829
P_GCC_GPLL9_OUT_MAIN,
29-
P_PCIE_0_PIPE_CLK,
3030
P_PCIE_1_PHY_AUX_CLK,
31-
P_PCIE_1_PIPE_CLK,
3231
P_SLEEP_CLK,
3332
P_UFS_PHY_RX_SYMBOL_0_CLK,
3433
P_UFS_PHY_RX_SYMBOL_1_CLK,
@@ -153,16 +152,6 @@ static const struct clk_parent_data gcc_parent_data_3[] = {
153152
{ .fw_name = "bi_tcxo" },
154153
};
155154

156-
static const struct parent_map gcc_parent_map_4[] = {
157-
{ P_PCIE_0_PIPE_CLK, 0 },
158-
{ P_BI_TCXO, 2 },
159-
};
160-
161-
static const struct clk_parent_data gcc_parent_data_4[] = {
162-
{ .fw_name = "pcie_0_pipe_clk", },
163-
{ .fw_name = "bi_tcxo", },
164-
};
165-
166155
static const struct parent_map gcc_parent_map_5[] = {
167156
{ P_PCIE_1_PHY_AUX_CLK, 0 },
168157
{ P_BI_TCXO, 2 },
@@ -173,16 +162,6 @@ static const struct clk_parent_data gcc_parent_data_5[] = {
173162
{ .fw_name = "bi_tcxo" },
174163
};
175164

176-
static const struct parent_map gcc_parent_map_6[] = {
177-
{ P_PCIE_1_PIPE_CLK, 0 },
178-
{ P_BI_TCXO, 2 },
179-
};
180-
181-
static const struct clk_parent_data gcc_parent_data_6[] = {
182-
{ .fw_name = "pcie_1_pipe_clk" },
183-
{ .fw_name = "bi_tcxo" },
184-
};
185-
186165
static const struct parent_map gcc_parent_map_7[] = {
187166
{ P_BI_TCXO, 0 },
188167
{ P_GCC_GPLL0_OUT_MAIN, 1 },
@@ -239,17 +218,16 @@ static const struct clk_parent_data gcc_parent_data_11[] = {
239218
{ .fw_name = "bi_tcxo" },
240219
};
241220

242-
static struct clk_regmap_mux gcc_pcie_0_pipe_clk_src = {
221+
static struct clk_regmap_phy_mux gcc_pcie_0_pipe_clk_src = {
243222
.reg = 0x7b060,
244-
.shift = 0,
245-
.width = 2,
246-
.parent_map = gcc_parent_map_4,
247223
.clkr = {
248224
.hw.init = &(struct clk_init_data){
249225
.name = "gcc_pcie_0_pipe_clk_src",
250-
.parent_data = gcc_parent_data_4,
251-
.num_parents = ARRAY_SIZE(gcc_parent_data_4),
252-
.ops = &clk_regmap_mux_closest_ops,
226+
.parent_data = &(const struct clk_parent_data){
227+
.fw_name = "pcie_0_pipe_clk",
228+
},
229+
.num_parents = 1,
230+
.ops = &clk_regmap_phy_mux_ops,
253231
},
254232
},
255233
};
@@ -269,17 +247,16 @@ static struct clk_regmap_mux gcc_pcie_1_phy_aux_clk_src = {
269247
},
270248
};
271249

272-
static struct clk_regmap_mux gcc_pcie_1_pipe_clk_src = {
250+
static struct clk_regmap_phy_mux gcc_pcie_1_pipe_clk_src = {
273251
.reg = 0x9d064,
274-
.shift = 0,
275-
.width = 2,
276-
.parent_map = gcc_parent_map_6,
277252
.clkr = {
278253
.hw.init = &(struct clk_init_data){
279254
.name = "gcc_pcie_1_pipe_clk_src",
280-
.parent_data = gcc_parent_data_6,
281-
.num_parents = ARRAY_SIZE(gcc_parent_data_6),
282-
.ops = &clk_regmap_mux_closest_ops,
255+
.parent_data = &(const struct clk_parent_data){
256+
.fw_name = "pcie_1_pipe_clk",
257+
},
258+
.num_parents = 1,
259+
.ops = &clk_regmap_phy_mux_ops,
283260
},
284261
},
285262
};

‎drivers/pci/controller/dwc/pcie-designware.h

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -97,6 +97,13 @@
9797
#define PCIE_MSI_INTR0_MASK 0x82C
9898
#define PCIE_MSI_INTR0_STATUS 0x830
9999

100+
#define GEN3_RELATED_OFF 0x890
101+
#define GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL BIT(0)
102+
#define GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS BIT(13)
103+
#define GEN3_RELATED_OFF_GEN3_EQ_DISABLE BIT(16)
104+
#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT 24
105+
#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK GENMASK(25, 24)
106+
100107
#define PCIE_PORT_MULTI_LANE_CTRL 0x8C0
101108
#define PORT_MLTI_UPCFG_SUPPORT BIT(7)
102109

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