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Merge tag 'drm-msm-next-2020-09-27' of https://gitlab.freedesktop.org/drm/msm into drm-next
* DSI support for sm8150/sm8250 * Support for per-process GPU pagetables (finally!) for a6xx. There are still some iommu/arm-smmu changes required to enable, without which it will fallback to the current single pgtable state. The first part (ie. what doesn't depend on drm side patches) is queued up for v5.10[1]. * DisplayPort support. Userspace DP compliance tool support is already merged in IGT[2] * The usual assortment of smaller fixes/cleanups Signed-off-by: Dave Airlie <[email protected]> From: Rob Clark <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/CAF6AEGvqjuzH=Po_9EzzFsp2Xq3tqJUTKfsA2g09XY7_+6Ypfw@mail.gmail.com
2 parents 32e4d9d + d1ea914 commit 91d0ca3

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‎Documentation/devicetree/bindings/display/msm/dsi.txt

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -90,6 +90,8 @@ Required properties:
9090
* "qcom,dsi-phy-14nm-660"
9191
* "qcom,dsi-phy-10nm"
9292
* "qcom,dsi-phy-10nm-8998"
93+
* "qcom,dsi-phy-7nm"
94+
* "qcom,dsi-phy-7nm-8150"
9395
- reg: Physical base address and length of the registers of PLL, PHY. Some
9496
revisions require the PHY regulator base address, whereas others require the
9597
PHY lane base address. See below for each PHY revision.
@@ -98,7 +100,7 @@ Required properties:
98100
* "dsi_pll"
99101
* "dsi_phy"
100102
* "dsi_phy_regulator"
101-
For DSI 14nm and 10nm PHYs:
103+
For DSI 14nm, 10nm and 7nm PHYs:
102104
* "dsi_pll"
103105
* "dsi_phy"
104106
* "dsi_phy_lane"
@@ -116,7 +118,7 @@ Required properties:
116118
- vcca-supply: phandle to vcca regulator device node
117119
For 14nm PHY:
118120
- vcca-supply: phandle to vcca regulator device node
119-
For 10nm PHY:
121+
For 10nm and 7nm PHY:
120122
- vdds-supply: phandle to vdds regulator device node
121123

122124
Optional properties:

‎drivers/gpu/drm/i915/display/intel_display.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -8168,7 +8168,7 @@ static void compute_m_n(unsigned int m, unsigned int n,
81688168
* which the devices expect also in synchronous clock mode.
81698169
*/
81708170
if (constant_n)
8171-
*ret_n = 0x8000;
8171+
*ret_n = DP_LINK_CONSTANT_N_VALUE;
81728172
else
81738173
*ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
81748174

‎drivers/gpu/drm/msm/Kconfig

Lines changed: 18 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -6,8 +6,8 @@ config DRM_MSM
66
depends on ARCH_QCOM || SOC_IMX5 || (ARM && COMPILE_TEST)
77
depends on OF && COMMON_CLK
88
depends on MMU
9-
depends on INTERCONNECT || !INTERCONNECT
109
depends on QCOM_OCMEM || QCOM_OCMEM=n
10+
select IOMMU_IO_PGTABLE
1111
select QCOM_MDT_LOADER if ARCH_QCOM
1212
select REGULATOR
1313
select DRM_KMS_HELPER
@@ -57,6 +57,15 @@ config DRM_MSM_HDMI_HDCP
5757
help
5858
Choose this option to enable HDCP state machine
5959

60+
config DRM_MSM_DP
61+
bool "Enable DisplayPort support in MSM DRM driver"
62+
depends on DRM_MSM
63+
default y
64+
help
65+
Compile in support for DP driver in MSM DRM driver. DP external
66+
display support is enabled through this config option. It can
67+
be primary or secondary display on device.
68+
6069
config DRM_MSM_DSI
6170
bool "Enable DSI support in MSM DRM driver"
6271
depends on DRM_MSM
@@ -110,3 +119,11 @@ config DRM_MSM_DSI_10NM_PHY
110119
default y
111120
help
112121
Choose this option if DSI PHY on SDM845 is used on the platform.
122+
123+
config DRM_MSM_DSI_7NM_PHY
124+
bool "Enable DSI 7nm PHY driver in MSM DRM (used by SM8150/SM8250)"
125+
depends on DRM_MSM_DSI
126+
default y
127+
help
128+
Choose this option if DSI PHY on SM8150/SM8250 is used on the
129+
platform.

‎drivers/gpu/drm/msm/Makefile

Lines changed: 17 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2,6 +2,7 @@
22
ccflags-y := -I $(srctree)/$(src)
33
ccflags-y += -I $(srctree)/$(src)/disp/dpu1
44
ccflags-$(CONFIG_DRM_MSM_DSI) += -I $(srctree)/$(src)/dsi
5+
ccflags-$(CONFIG_DRM_MSM_DP) += -I $(srctree)/$(src)/dp
56

67
msm-y := \
78
adreno/adreno_device.o \
@@ -95,10 +96,23 @@ msm-y := \
9596
msm_gpu_tracepoints.o \
9697
msm_gpummu.o
9798

98-
msm-$(CONFIG_DEBUG_FS) += adreno/a5xx_debugfs.o
99+
msm-$(CONFIG_DEBUG_FS) += adreno/a5xx_debugfs.o \
100+
dp/dp_debug.o
99101

100102
msm-$(CONFIG_DRM_MSM_GPU_STATE) += adreno/a6xx_gpu_state.o
101103

104+
msm-$(CONFIG_DRM_MSM_DP)+= dp/dp_aux.o \
105+
dp/dp_catalog.o \
106+
dp/dp_ctrl.o \
107+
dp/dp_display.o \
108+
dp/dp_drm.o \
109+
dp/dp_hpd.o \
110+
dp/dp_link.o \
111+
dp/dp_panel.o \
112+
dp/dp_parser.o \
113+
dp/dp_power.o \
114+
dp/dp_audio.o
115+
102116
msm-$(CONFIG_DRM_FBDEV_EMULATION) += msm_fbdev.o
103117
msm-$(CONFIG_COMMON_CLK) += disp/mdp4/mdp4_lvds_pll.o
104118
msm-$(CONFIG_COMMON_CLK) += hdmi/hdmi_pll_8960.o
@@ -119,13 +133,15 @@ msm-$(CONFIG_DRM_MSM_DSI_20NM_PHY) += dsi/phy/dsi_phy_20nm.o
119133
msm-$(CONFIG_DRM_MSM_DSI_28NM_8960_PHY) += dsi/phy/dsi_phy_28nm_8960.o
120134
msm-$(CONFIG_DRM_MSM_DSI_14NM_PHY) += dsi/phy/dsi_phy_14nm.o
121135
msm-$(CONFIG_DRM_MSM_DSI_10NM_PHY) += dsi/phy/dsi_phy_10nm.o
136+
msm-$(CONFIG_DRM_MSM_DSI_7NM_PHY) += dsi/phy/dsi_phy_7nm.o
122137

123138
ifeq ($(CONFIG_DRM_MSM_DSI_PLL),y)
124139
msm-y += dsi/pll/dsi_pll.o
125140
msm-$(CONFIG_DRM_MSM_DSI_28NM_PHY) += dsi/pll/dsi_pll_28nm.o
126141
msm-$(CONFIG_DRM_MSM_DSI_28NM_8960_PHY) += dsi/pll/dsi_pll_28nm_8960.o
127142
msm-$(CONFIG_DRM_MSM_DSI_14NM_PHY) += dsi/pll/dsi_pll_14nm.o
128143
msm-$(CONFIG_DRM_MSM_DSI_10NM_PHY) += dsi/pll/dsi_pll_10nm.o
144+
msm-$(CONFIG_DRM_MSM_DSI_7NM_PHY) += dsi/pll/dsi_pll_7nm.o
129145
endif
130146

131147
obj-$(CONFIG_DRM_MSM) += msm.o

‎drivers/gpu/drm/msm/adreno/a2xx_gpu.c

Lines changed: 50 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -10,6 +10,48 @@ extern bool hang_debug;
1010
static void a2xx_dump(struct msm_gpu *gpu);
1111
static bool a2xx_idle(struct msm_gpu *gpu);
1212

13+
static void a2xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
14+
{
15+
struct msm_drm_private *priv = gpu->dev->dev_private;
16+
struct msm_ringbuffer *ring = submit->ring;
17+
unsigned int i;
18+
19+
for (i = 0; i < submit->nr_cmds; i++) {
20+
switch (submit->cmd[i].type) {
21+
case MSM_SUBMIT_CMD_IB_TARGET_BUF:
22+
/* ignore IB-targets */
23+
break;
24+
case MSM_SUBMIT_CMD_CTX_RESTORE_BUF:
25+
/* ignore if there has not been a ctx switch: */
26+
if (priv->lastctx == submit->queue->ctx)
27+
break;
28+
fallthrough;
29+
case MSM_SUBMIT_CMD_BUF:
30+
OUT_PKT3(ring, CP_INDIRECT_BUFFER_PFD, 2);
31+
OUT_RING(ring, lower_32_bits(submit->cmd[i].iova));
32+
OUT_RING(ring, submit->cmd[i].size);
33+
OUT_PKT2(ring);
34+
break;
35+
}
36+
}
37+
38+
OUT_PKT0(ring, REG_AXXX_CP_SCRATCH_REG2, 1);
39+
OUT_RING(ring, submit->seqno);
40+
41+
/* wait for idle before cache flush/interrupt */
42+
OUT_PKT3(ring, CP_WAIT_FOR_IDLE, 1);
43+
OUT_RING(ring, 0x00000000);
44+
45+
OUT_PKT3(ring, CP_EVENT_WRITE, 3);
46+
OUT_RING(ring, CACHE_FLUSH_TS);
47+
OUT_RING(ring, rbmemptr(ring, fence));
48+
OUT_RING(ring, submit->seqno);
49+
OUT_PKT3(ring, CP_INTERRUPT, 1);
50+
OUT_RING(ring, 0x80000000);
51+
52+
adreno_flush(gpu, ring, REG_AXXX_CP_RB_WPTR);
53+
}
54+
1355
static bool a2xx_me_init(struct msm_gpu *gpu)
1456
{
1557
struct msm_ringbuffer *ring = gpu->rb[0];
@@ -53,7 +95,7 @@ static bool a2xx_me_init(struct msm_gpu *gpu)
5395
OUT_PKT3(ring, CP_SET_PROTECTED_MODE, 1);
5496
OUT_RING(ring, 1);
5597

56-
gpu->funcs->flush(gpu, ring);
98+
adreno_flush(gpu, ring, REG_AXXX_CP_RB_WPTR);
5799
return a2xx_idle(gpu);
58100
}
59101

@@ -421,16 +463,11 @@ a2xx_create_address_space(struct msm_gpu *gpu, struct platform_device *pdev)
421463
return aspace;
422464
}
423465

424-
/* Register offset defines for A2XX - copy of A3XX */
425-
static const unsigned int a2xx_register_offsets[REG_ADRENO_REGISTER_MAX] = {
426-
REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_BASE, REG_AXXX_CP_RB_BASE),
427-
REG_ADRENO_SKIP(REG_ADRENO_CP_RB_BASE_HI),
428-
REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_RPTR_ADDR, REG_AXXX_CP_RB_RPTR_ADDR),
429-
REG_ADRENO_SKIP(REG_ADRENO_CP_RB_RPTR_ADDR_HI),
430-
REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_RPTR, REG_AXXX_CP_RB_RPTR),
431-
REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_WPTR, REG_AXXX_CP_RB_WPTR),
432-
REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_CNTL, REG_AXXX_CP_RB_CNTL),
433-
};
466+
static u32 a2xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
467+
{
468+
ring->memptrs->rptr = gpu_read(gpu, REG_AXXX_CP_RB_RPTR);
469+
return ring->memptrs->rptr;
470+
}
434471

435472
static const struct adreno_gpu_funcs funcs = {
436473
.base = {
@@ -439,8 +476,7 @@ static const struct adreno_gpu_funcs funcs = {
439476
.pm_suspend = msm_gpu_pm_suspend,
440477
.pm_resume = msm_gpu_pm_resume,
441478
.recover = a2xx_recover,
442-
.submit = adreno_submit,
443-
.flush = adreno_flush,
479+
.submit = a2xx_submit,
444480
.active_ring = adreno_active_ring,
445481
.irq = a2xx_irq,
446482
.destroy = a2xx_destroy,
@@ -450,6 +486,7 @@ static const struct adreno_gpu_funcs funcs = {
450486
.gpu_state_get = a2xx_gpu_state_get,
451487
.gpu_state_put = adreno_gpu_state_put,
452488
.create_address_space = a2xx_create_address_space,
489+
.get_rptr = a2xx_get_rptr,
453490
},
454491
};
455492

@@ -491,8 +528,6 @@ struct msm_gpu *a2xx_gpu_init(struct drm_device *dev)
491528
else
492529
adreno_gpu->registers = a220_registers;
493530

494-
adreno_gpu->reg_offsets = a2xx_register_offsets;
495-
496531
ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 1);
497532
if (ret)
498533
goto fail;

‎drivers/gpu/drm/msm/adreno/a3xx_gpu.c

Lines changed: 63 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -28,6 +28,61 @@ extern bool hang_debug;
2828
static void a3xx_dump(struct msm_gpu *gpu);
2929
static bool a3xx_idle(struct msm_gpu *gpu);
3030

31+
static void a3xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
32+
{
33+
struct msm_drm_private *priv = gpu->dev->dev_private;
34+
struct msm_ringbuffer *ring = submit->ring;
35+
unsigned int i;
36+
37+
for (i = 0; i < submit->nr_cmds; i++) {
38+
switch (submit->cmd[i].type) {
39+
case MSM_SUBMIT_CMD_IB_TARGET_BUF:
40+
/* ignore IB-targets */
41+
break;
42+
case MSM_SUBMIT_CMD_CTX_RESTORE_BUF:
43+
/* ignore if there has not been a ctx switch: */
44+
if (priv->lastctx == submit->queue->ctx)
45+
break;
46+
fallthrough;
47+
case MSM_SUBMIT_CMD_BUF:
48+
OUT_PKT3(ring, CP_INDIRECT_BUFFER_PFD, 2);
49+
OUT_RING(ring, lower_32_bits(submit->cmd[i].iova));
50+
OUT_RING(ring, submit->cmd[i].size);
51+
OUT_PKT2(ring);
52+
break;
53+
}
54+
}
55+
56+
OUT_PKT0(ring, REG_AXXX_CP_SCRATCH_REG2, 1);
57+
OUT_RING(ring, submit->seqno);
58+
59+
/* Flush HLSQ lazy updates to make sure there is nothing
60+
* pending for indirect loads after the timestamp has
61+
* passed:
62+
*/
63+
OUT_PKT3(ring, CP_EVENT_WRITE, 1);
64+
OUT_RING(ring, HLSQ_FLUSH);
65+
66+
/* wait for idle before cache flush/interrupt */
67+
OUT_PKT3(ring, CP_WAIT_FOR_IDLE, 1);
68+
OUT_RING(ring, 0x00000000);
69+
70+
/* BIT(31) of CACHE_FLUSH_TS triggers CACHE_FLUSH_TS IRQ from GPU */
71+
OUT_PKT3(ring, CP_EVENT_WRITE, 3);
72+
OUT_RING(ring, CACHE_FLUSH_TS | BIT(31));
73+
OUT_RING(ring, rbmemptr(ring, fence));
74+
OUT_RING(ring, submit->seqno);
75+
76+
#if 0
77+
/* Dummy set-constant to trigger context rollover */
78+
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
79+
OUT_RING(ring, CP_REG(REG_A3XX_HLSQ_CL_KERNEL_GROUP_X_REG));
80+
OUT_RING(ring, 0x00000000);
81+
#endif
82+
83+
adreno_flush(gpu, ring, REG_AXXX_CP_RB_WPTR);
84+
}
85+
3186
static bool a3xx_me_init(struct msm_gpu *gpu)
3287
{
3388
struct msm_ringbuffer *ring = gpu->rb[0];
@@ -51,7 +106,7 @@ static bool a3xx_me_init(struct msm_gpu *gpu)
51106
OUT_RING(ring, 0x00000000);
52107
OUT_RING(ring, 0x00000000);
53108

54-
gpu->funcs->flush(gpu, ring);
109+
adreno_flush(gpu, ring, REG_AXXX_CP_RB_WPTR);
55110
return a3xx_idle(gpu);
56111
}
57112

@@ -423,16 +478,11 @@ static struct msm_gpu_state *a3xx_gpu_state_get(struct msm_gpu *gpu)
423478
return state;
424479
}
425480

426-
/* Register offset defines for A3XX */
427-
static const unsigned int a3xx_register_offsets[REG_ADRENO_REGISTER_MAX] = {
428-
REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_BASE, REG_AXXX_CP_RB_BASE),
429-
REG_ADRENO_SKIP(REG_ADRENO_CP_RB_BASE_HI),
430-
REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_RPTR_ADDR, REG_AXXX_CP_RB_RPTR_ADDR),
431-
REG_ADRENO_SKIP(REG_ADRENO_CP_RB_RPTR_ADDR_HI),
432-
REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_RPTR, REG_AXXX_CP_RB_RPTR),
433-
REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_WPTR, REG_AXXX_CP_RB_WPTR),
434-
REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_CNTL, REG_AXXX_CP_RB_CNTL),
435-
};
481+
static u32 a3xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
482+
{
483+
ring->memptrs->rptr = gpu_read(gpu, REG_AXXX_CP_RB_RPTR);
484+
return ring->memptrs->rptr;
485+
}
436486

437487
static const struct adreno_gpu_funcs funcs = {
438488
.base = {
@@ -441,8 +491,7 @@ static const struct adreno_gpu_funcs funcs = {
441491
.pm_suspend = msm_gpu_pm_suspend,
442492
.pm_resume = msm_gpu_pm_resume,
443493
.recover = a3xx_recover,
444-
.submit = adreno_submit,
445-
.flush = adreno_flush,
494+
.submit = a3xx_submit,
446495
.active_ring = adreno_active_ring,
447496
.irq = a3xx_irq,
448497
.destroy = a3xx_destroy,
@@ -452,6 +501,7 @@ static const struct adreno_gpu_funcs funcs = {
452501
.gpu_state_get = a3xx_gpu_state_get,
453502
.gpu_state_put = adreno_gpu_state_put,
454503
.create_address_space = adreno_iommu_create_address_space,
504+
.get_rptr = a3xx_get_rptr,
455505
},
456506
};
457507

@@ -490,7 +540,6 @@ struct msm_gpu *a3xx_gpu_init(struct drm_device *dev)
490540
gpu->num_perfcntrs = ARRAY_SIZE(perfcntrs);
491541

492542
adreno_gpu->registers = a3xx_registers;
493-
adreno_gpu->reg_offsets = a3xx_register_offsets;
494543

495544
ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 1);
496545
if (ret)

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