@@ -226,6 +226,14 @@ static const struct llcc_slice_config sm6350_data[] = {
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{ LLCC_MODPE , 29 , 64 , 1 , 1 , 0xFFF , 0x0 , 0 , 0 , 0 , 0 , 1 , 0 },
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};
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+ static const struct llcc_slice_config sm7150_data [] = {
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+ { LLCC_CPUSS , 1 , 512 , 1 , 0 , 0xF , 0x0 , 0 , 0 , 0 , 1 , 1 },
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+ { LLCC_MDM , 8 , 128 , 2 , 0 , 0xF , 0x0 , 0 , 0 , 0 , 1 , 0 },
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+ { LLCC_GPUHTW , 11 , 256 , 1 , 1 , 0xF , 0x0 , 0 , 0 , 0 , 1 , 0 },
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+ { LLCC_GPU , 12 , 256 , 1 , 1 , 0xF , 0x0 , 0 , 0 , 0 , 1 , 0 },
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+ { LLCC_NPU , 23 , 512 , 1 , 0 , 0xF , 0x0 , 0 , 0 , 0 , 1 , 0 },
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+ };
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+
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static const struct llcc_slice_config sm8150_data [] = {
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{ LLCC_CPUSS , 1 , 3072 , 1 , 1 , 0xFFF , 0x0 , 0 , 0 , 0 , 1 , 1 },
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{ LLCC_VIDSC0 , 2 , 512 , 2 , 1 , 0xFFF , 0x0 , 0 , 0 , 0 , 1 , 0 },
@@ -464,6 +472,14 @@ static const struct qcom_llcc_config sm6350_cfg = {
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.edac_reg_offset = & llcc_v1_edac_reg_offset ,
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};
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+ static const struct qcom_llcc_config sm7150_cfg = {
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+ .sct_data = sm7150_data ,
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+ .size = ARRAY_SIZE (sm7150_data ),
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+ .need_llcc_cfg = true,
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+ .reg_offset = llcc_v1_reg_offset ,
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+ .edac_reg_offset = & llcc_v1_edac_reg_offset ,
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+ };
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+
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static const struct qcom_llcc_config sm8150_cfg = {
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.sct_data = sm8150_data ,
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.size = ARRAY_SIZE (sm8150_data ),
@@ -1041,6 +1057,7 @@ static const struct of_device_id qcom_llcc_of_match[] = {
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{ .compatible = "qcom,sc8280xp-llcc" , .data = & sc8280xp_cfg },
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{ .compatible = "qcom,sdm845-llcc" , .data = & sdm845_cfg },
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{ .compatible = "qcom,sm6350-llcc" , .data = & sm6350_cfg },
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+ { .compatible = "qcom,sm7150-llcc" , .data = & sm7150_cfg },
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{ .compatible = "qcom,sm8150-llcc" , .data = & sm8150_cfg },
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{ .compatible = "qcom,sm8250-llcc" , .data = & sm8250_cfg },
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{ .compatible = "qcom,sm8350-llcc" , .data = & sm8350_cfg },
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