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*/
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#include <linux/clk-provider.h>
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+ #include <linux/interconnect-provider.h>
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#include <linux/mod_devicetable.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <dt-bindings/clock/qcom,ipq5332-gcc.h>
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+ #include <dt-bindings/interconnect/qcom,ipq5332.h>
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#include "clk-alpha-pll.h"
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#include "clk-branch.h"
@@ -126,17 +128,6 @@ static struct clk_alpha_pll gpll4_main = {
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.parent_data = & gcc_parent_data_xo ,
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.num_parents = 1 ,
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.ops = & clk_alpha_pll_stromer_ops ,
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- /*
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- * There are no consumers for this GPLL in kernel yet,
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- * (will be added soon), so the clock framework
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- * disables this source. But some of the clocks
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- * initialized by boot loaders uses this source. So we
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- * need to keep this clock ON. Add the
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- * CLK_IGNORE_UNUSED flag so the clock will not be
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- * disabled. Once the consumer in kernel is added, we
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- * can get rid of this flag.
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- */
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- .flags = CLK_IGNORE_UNUSED ,
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},
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},
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};
@@ -3629,6 +3620,24 @@ static const struct qcom_reset_map gcc_ipq5332_resets[] = {
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[GCC_UNIPHY1_XPCS_ARES ] = { 0x16060 },
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};
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+ #define IPQ_APPS_ID 5332 /* some unique value */
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+
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+ static struct qcom_icc_hws_data icc_ipq5332_hws [] = {
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+ { MASTER_SNOC_PCIE3_1_M , SLAVE_SNOC_PCIE3_1_M , GCC_SNOC_PCIE3_1LANE_M_CLK },
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+ { MASTER_ANOC_PCIE3_1_S , SLAVE_ANOC_PCIE3_1_S , GCC_SNOC_PCIE3_1LANE_S_CLK },
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+ { MASTER_SNOC_PCIE3_2_M , SLAVE_SNOC_PCIE3_2_M , GCC_SNOC_PCIE3_2LANE_M_CLK },
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+ { MASTER_ANOC_PCIE3_2_S , SLAVE_ANOC_PCIE3_2_S , GCC_SNOC_PCIE3_2LANE_S_CLK },
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+ { MASTER_SNOC_USB , SLAVE_SNOC_USB , GCC_SNOC_USB_CLK },
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+ { MASTER_NSSNOC_NSSCC , SLAVE_NSSNOC_NSSCC , GCC_NSSNOC_NSSCC_CLK },
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+ { MASTER_NSSNOC_SNOC_0 , SLAVE_NSSNOC_SNOC_0 , GCC_NSSNOC_SNOC_CLK },
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+ { MASTER_NSSNOC_SNOC_1 , SLAVE_NSSNOC_SNOC_1 , GCC_NSSNOC_SNOC_1_CLK },
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+ { MASTER_NSSNOC_ATB , SLAVE_NSSNOC_ATB , GCC_NSSNOC_ATB_CLK },
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+ { MASTER_NSSNOC_PCNOC_1 , SLAVE_NSSNOC_PCNOC_1 , GCC_NSSNOC_PCNOC_1_CLK },
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+ { MASTER_NSSNOC_QOSGEN_REF , SLAVE_NSSNOC_QOSGEN_REF , GCC_NSSNOC_QOSGEN_REF_CLK },
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+ { MASTER_NSSNOC_TIMEOUT_REF , SLAVE_NSSNOC_TIMEOUT_REF , GCC_NSSNOC_TIMEOUT_REF_CLK },
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+ { MASTER_NSSNOC_XO_DCD , SLAVE_NSSNOC_XO_DCD , GCC_NSSNOC_XO_DCD_CLK },
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+ };
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+
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static const struct regmap_config gcc_ipq5332_regmap_config = {
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.reg_bits = 32 ,
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.reg_stride = 4 ,
@@ -3657,6 +3666,9 @@ static const struct qcom_cc_desc gcc_ipq5332_desc = {
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.num_resets = ARRAY_SIZE (gcc_ipq5332_resets ),
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.clk_hws = gcc_ipq5332_hws ,
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.num_clk_hws = ARRAY_SIZE (gcc_ipq5332_hws ),
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+ .icc_hws = icc_ipq5332_hws ,
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+ .num_icc_hws = ARRAY_SIZE (icc_ipq5332_hws ),
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+ .icc_first_node_id = IPQ_APPS_ID ,
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};
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static int gcc_ipq5332_probe (struct platform_device * pdev )
@@ -3675,6 +3687,7 @@ static struct platform_driver gcc_ipq5332_driver = {
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.driver = {
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.name = "gcc-ipq5332" ,
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.of_match_table = gcc_ipq5332_match_table ,
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+ .sync_state = icc_sync_state ,
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},
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};
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