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quic-kdybcioandersson
quic-kdybcio
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soc: qcom: llcc: Flip the manual slice configuration condition
Commit c14e64b ("soc: qcom: llcc: Support chipsets that can write to llcc") made the code not configure certain registers on SDM845 due to firmware security policies. That turned out only to concern SDM845, but the condition was chosen such that all other entries (for SoCs that didnot need it) were required to set .need_llcc_cfg = true. Flip the condition, so the default is "doesn't need the workaround". Signed-off-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] [bjorn: Dropped a few newly added need_llcc_cfg uses] Signed-off-by: Bjorn Andersson <[email protected]>
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‎drivers/soc/qcom/llcc-qcom.c

Lines changed: 4 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -139,7 +139,7 @@ struct qcom_llcc_config {
139139
u32 max_cap_shift; /* instead of ATTR1_MAX_CAP_SHIFT */
140140
u32 num_banks;
141141
int size;
142-
bool need_llcc_cfg;
142+
bool skip_llcc_cfg;
143143
bool no_edac;
144144
};
145145

@@ -3142,7 +3142,6 @@ static const struct qcom_llcc_config qcs615_cfg[] = {
31423142
{
31433143
.sct_data = qcs615_data,
31443144
.size = ARRAY_SIZE(qcs615_data),
3145-
.need_llcc_cfg = true,
31463145
.reg_offset = llcc_v1_reg_offset,
31473146
.edac_reg_offset = &llcc_v1_edac_reg_offset,
31483147
},
@@ -3152,7 +3151,6 @@ static const struct qcom_llcc_config qcs8300_cfg[] = {
31523151
{
31533152
.sct_data = qcs8300_data,
31543153
.size = ARRAY_SIZE(qcs8300_data),
3155-
.need_llcc_cfg = true,
31563154
.reg_offset = llcc_v2_1_reg_offset,
31573155
.edac_reg_offset = &llcc_v2_1_edac_reg_offset,
31583156
.num_banks = 4,
@@ -3163,28 +3161,24 @@ static const struct qcom_llcc_config qdu1000_cfg[] = {
31633161
{
31643162
.sct_data = qdu1000_data_8ch,
31653163
.size = ARRAY_SIZE(qdu1000_data_8ch),
3166-
.need_llcc_cfg = true,
31673164
.reg_offset = llcc_v2_1_reg_offset,
31683165
.edac_reg_offset = &llcc_v2_1_edac_reg_offset,
31693166
},
31703167
{
31713168
.sct_data = qdu1000_data_4ch,
31723169
.size = ARRAY_SIZE(qdu1000_data_4ch),
3173-
.need_llcc_cfg = true,
31743170
.reg_offset = llcc_v2_1_reg_offset,
31753171
.edac_reg_offset = &llcc_v2_1_edac_reg_offset,
31763172
},
31773173
{
31783174
.sct_data = qdu1000_data_4ch,
31793175
.size = ARRAY_SIZE(qdu1000_data_4ch),
3180-
.need_llcc_cfg = true,
31813176
.reg_offset = llcc_v2_1_reg_offset,
31823177
.edac_reg_offset = &llcc_v2_1_edac_reg_offset,
31833178
},
31843179
{
31853180
.sct_data = qdu1000_data_2ch,
31863181
.size = ARRAY_SIZE(qdu1000_data_2ch),
3187-
.need_llcc_cfg = true,
31883182
.reg_offset = llcc_v2_1_reg_offset,
31893183
.edac_reg_offset = &llcc_v2_1_edac_reg_offset,
31903184
},
@@ -3194,7 +3188,6 @@ static const struct qcom_llcc_config sa8775p_cfg[] = {
31943188
{
31953189
.sct_data = sa8775p_data,
31963190
.size = ARRAY_SIZE(sa8775p_data),
3197-
.need_llcc_cfg = true,
31983191
.reg_offset = llcc_v2_1_reg_offset,
31993192
.edac_reg_offset = &llcc_v2_1_edac_reg_offset,
32003193
},
@@ -3204,7 +3197,6 @@ static const struct qcom_llcc_config sar1130p_cfg[] = {
32043197
{
32053198
.sct_data = sar1130p_data,
32063199
.size = ARRAY_SIZE(sar1130p_data),
3207-
.need_llcc_cfg = true,
32083200
.reg_offset = llcc_v2_1_reg_offset,
32093201
.edac_reg_offset = &llcc_v2_1_edac_reg_offset,
32103202
.max_cap_shift = 14,
@@ -3216,7 +3208,6 @@ static const struct qcom_llcc_config sar2130p_cfg[] = {
32163208
{
32173209
.sct_data = sar2130p_data,
32183210
.size = ARRAY_SIZE(sar2130p_data),
3219-
.need_llcc_cfg = true,
32203211
.reg_offset = llcc_v2_1_reg_offset,
32213212
.edac_reg_offset = &llcc_v2_1_edac_reg_offset,
32223213
.max_cap_shift = 14,
@@ -3228,7 +3219,6 @@ static const struct qcom_llcc_config sc7180_cfg[] = {
32283219
{
32293220
.sct_data = sc7180_data,
32303221
.size = ARRAY_SIZE(sc7180_data),
3231-
.need_llcc_cfg = true,
32323222
.reg_offset = llcc_v1_reg_offset,
32333223
.edac_reg_offset = &llcc_v1_edac_reg_offset,
32343224
},
@@ -3238,7 +3228,6 @@ static const struct qcom_llcc_config sc7280_cfg[] = {
32383228
{
32393229
.sct_data = sc7280_data,
32403230
.size = ARRAY_SIZE(sc7280_data),
3241-
.need_llcc_cfg = true,
32423231
.reg_offset = llcc_v1_reg_offset,
32433232
.edac_reg_offset = &llcc_v1_edac_reg_offset,
32443233
},
@@ -3248,7 +3237,6 @@ static const struct qcom_llcc_config sc8180x_cfg[] = {
32483237
{
32493238
.sct_data = sc8180x_data,
32503239
.size = ARRAY_SIZE(sc8180x_data),
3251-
.need_llcc_cfg = true,
32523240
.reg_offset = llcc_v1_reg_offset,
32533241
.edac_reg_offset = &llcc_v1_edac_reg_offset,
32543242
},
@@ -3258,7 +3246,6 @@ static const struct qcom_llcc_config sc8280xp_cfg[] = {
32583246
{
32593247
.sct_data = sc8280xp_data,
32603248
.size = ARRAY_SIZE(sc8280xp_data),
3261-
.need_llcc_cfg = true,
32623249
.reg_offset = llcc_v1_reg_offset,
32633250
.edac_reg_offset = &llcc_v1_edac_reg_offset,
32643251
},
@@ -3268,7 +3255,7 @@ static const struct qcom_llcc_config sdm845_cfg[] = {
32683255
{
32693256
.sct_data = sdm845_data,
32703257
.size = ARRAY_SIZE(sdm845_data),
3271-
.need_llcc_cfg = false,
3258+
.skip_llcc_cfg = true,
32723259
.reg_offset = llcc_v1_reg_offset,
32733260
.edac_reg_offset = &llcc_v1_edac_reg_offset,
32743261
.no_edac = true,
@@ -3279,7 +3266,6 @@ static const struct qcom_llcc_config sm6350_cfg[] = {
32793266
{
32803267
.sct_data = sm6350_data,
32813268
.size = ARRAY_SIZE(sm6350_data),
3282-
.need_llcc_cfg = true,
32833269
.reg_offset = llcc_v1_reg_offset,
32843270
.edac_reg_offset = &llcc_v1_edac_reg_offset,
32853271
},
@@ -3289,7 +3275,6 @@ static const struct qcom_llcc_config sm7150_cfg[] = {
32893275
{
32903276
.sct_data = sm7150_data,
32913277
.size = ARRAY_SIZE(sm7150_data),
3292-
.need_llcc_cfg = true,
32933278
.reg_offset = llcc_v1_reg_offset,
32943279
.edac_reg_offset = &llcc_v1_edac_reg_offset,
32953280
},
@@ -3299,7 +3284,6 @@ static const struct qcom_llcc_config sm8150_cfg[] = {
32993284
{
33003285
.sct_data = sm8150_data,
33013286
.size = ARRAY_SIZE(sm8150_data),
3302-
.need_llcc_cfg = true,
33033287
.reg_offset = llcc_v1_reg_offset,
33043288
.edac_reg_offset = &llcc_v1_edac_reg_offset,
33053289
},
@@ -3309,7 +3293,6 @@ static const struct qcom_llcc_config sm8250_cfg[] = {
33093293
{
33103294
.sct_data = sm8250_data,
33113295
.size = ARRAY_SIZE(sm8250_data),
3312-
.need_llcc_cfg = true,
33133296
.reg_offset = llcc_v1_reg_offset,
33143297
.edac_reg_offset = &llcc_v1_edac_reg_offset,
33153298
},
@@ -3319,7 +3302,6 @@ static const struct qcom_llcc_config sm8350_cfg[] = {
33193302
{
33203303
.sct_data = sm8350_data,
33213304
.size = ARRAY_SIZE(sm8350_data),
3322-
.need_llcc_cfg = true,
33233305
.reg_offset = llcc_v1_reg_offset,
33243306
.edac_reg_offset = &llcc_v1_edac_reg_offset,
33253307
},
@@ -3329,7 +3311,6 @@ static const struct qcom_llcc_config sm8450_cfg[] = {
33293311
{
33303312
.sct_data = sm8450_data,
33313313
.size = ARRAY_SIZE(sm8450_data),
3332-
.need_llcc_cfg = true,
33333314
.reg_offset = llcc_v2_1_reg_offset,
33343315
.edac_reg_offset = &llcc_v2_1_edac_reg_offset,
33353316
},
@@ -3339,7 +3320,6 @@ static const struct qcom_llcc_config sm8550_cfg[] = {
33393320
{
33403321
.sct_data = sm8550_data,
33413322
.size = ARRAY_SIZE(sm8550_data),
3342-
.need_llcc_cfg = true,
33433323
.reg_offset = llcc_v2_1_reg_offset,
33443324
.edac_reg_offset = &llcc_v2_1_edac_reg_offset,
33453325
},
@@ -3349,7 +3329,6 @@ static const struct qcom_llcc_config sm8650_cfg[] = {
33493329
{
33503330
.sct_data = sm8650_data,
33513331
.size = ARRAY_SIZE(sm8650_data),
3352-
.need_llcc_cfg = true,
33533332
.reg_offset = llcc_v2_1_reg_offset,
33543333
.edac_reg_offset = &llcc_v2_1_edac_reg_offset,
33553334
},
@@ -3359,7 +3338,6 @@ static const struct qcom_llcc_config x1e80100_cfg[] = {
33593338
{
33603339
.sct_data = x1e80100_data,
33613340
.size = ARRAY_SIZE(x1e80100_data),
3362-
.need_llcc_cfg = true,
33633341
.reg_offset = llcc_v2_1_reg_offset,
33643342
.edac_reg_offset = &llcc_v2_1_edac_reg_offset,
33653343
},
@@ -3734,7 +3712,8 @@ static int _qcom_llcc_cfg_program(const struct llcc_slice_config *config,
37343712
return ret;
37353713
}
37363714

3737-
if (cfg->need_llcc_cfg) {
3715+
/* At least SDM845 disallows non-secure writes to these registers */
3716+
if (!cfg->skip_llcc_cfg) {
37383717
u32 disable_cap_alloc, retain_pc;
37393718

37403719
disable_cap_alloc = config->dis_cap_alloc << config->slice_id;

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