Skip to content

Commit 92fd171

Browse files
shaoyunlalexdeucher
authored andcommitted
drm/amd/amdgpu: Increase MES log buffer to dump mes scratch data
MES internal scratch data is useful for mes debug, it can only located in VRAM, change the allocation type and increase size for mes 11 Signed-off-by: shaoyunl <[email protected]> Acked-by: Feifei Xu <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
1 parent 84a2947 commit 92fd171

File tree

3 files changed

+13
-2
lines changed

3 files changed

+13
-2
lines changed

drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -104,7 +104,7 @@ static int amdgpu_mes_event_log_init(struct amdgpu_device *adev)
104104
return 0;
105105

106106
r = amdgpu_bo_create_kernel(adev, adev->mes.event_log_size, PAGE_SIZE,
107-
AMDGPU_GEM_DOMAIN_GTT,
107+
AMDGPU_GEM_DOMAIN_VRAM,
108108
&adev->mes.event_log_gpu_obj,
109109
&adev->mes.event_log_gpu_addr,
110110
&adev->mes.event_log_cpu_addr);

drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -40,6 +40,7 @@
4040
#define AMDGPU_MES_VERSION_MASK 0x00000fff
4141
#define AMDGPU_MES_API_VERSION_MASK 0x00fff000
4242
#define AMDGPU_MES_FEAT_VERSION_MASK 0xff000000
43+
#define AMDGPU_MES_MSCRATCH_SIZE 0x8000
4344

4445
enum amdgpu_mes_priority_level {
4546
AMDGPU_MES_PRIORITY_LEVEL_LOW = 0,

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

Lines changed: 11 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -908,6 +908,16 @@ static void mes_v11_0_enable(struct amdgpu_device *adev, bool enable)
908908
uint32_t pipe, data = 0;
909909

910910
if (enable) {
911+
if (amdgpu_mes_log_enable) {
912+
WREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_LO,
913+
lower_32_bits(adev->mes.event_log_gpu_addr + AMDGPU_MES_LOG_BUFFER_SIZE));
914+
WREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_HI,
915+
upper_32_bits(adev->mes.event_log_gpu_addr + AMDGPU_MES_LOG_BUFFER_SIZE));
916+
dev_info(adev->dev, "Setup CP MES MSCRATCH address : 0x%x. 0x%x\n",
917+
RREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_HI),
918+
RREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_LO));
919+
}
920+
911921
data = RREG32_SOC15(GC, 0, regCP_MES_CNTL);
912922
data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1);
913923
data = REG_SET_FIELD(data, CP_MES_CNTL,
@@ -1370,7 +1380,7 @@ static int mes_v11_0_sw_init(struct amdgpu_ip_block *ip_block)
13701380
adev->mes.kiq_hw_init = &mes_v11_0_kiq_hw_init;
13711381
adev->mes.kiq_hw_fini = &mes_v11_0_kiq_hw_fini;
13721382

1373-
adev->mes.event_log_size = AMDGPU_MES_LOG_BUFFER_SIZE;
1383+
adev->mes.event_log_size = AMDGPU_MES_LOG_BUFFER_SIZE + AMDGPU_MES_MSCRATCH_SIZE;
13741384

13751385
r = amdgpu_mes_init(adev);
13761386
if (r)

0 commit comments

Comments
 (0)