Skip to content

Commit 9320c7d

Browse files
bebarinobebarino
committed
Merge tag 'v5.5-rockchip-clk-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-rockchip
Pull Rockchip clk driver updates from Heiko Stuebner: Adding a missing static declaration for clk_half_divider_ops and a number of improvements for the px30 clock tree. * tag 'v5.5-rockchip-clk-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: protect the pclk_usb_grf as critical on px30 clk: rockchip: add video-related niu clocks as critical on px30 clk: rockchip: move px30 critical clocks to correct clock controller clk: rockchip: Add div50 clocks for px30 sdmmc, emmc, sdio and nandc clk: rockchip: Add div50 clock-ids for sdmmc on px30 and nandc clk: rockchip: make clk_half_divider_ops static
2 parents 54ecb8f + 3b0b4eb commit 9320c7d

File tree

3 files changed

+59
-16
lines changed

3 files changed

+59
-16
lines changed

‎drivers/clk/rockchip/clk-half-divider.c

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -139,12 +139,11 @@ static int clk_half_divider_set_rate(struct clk_hw *hw, unsigned long rate,
139139
return 0;
140140
}
141141

142-
const struct clk_ops clk_half_divider_ops = {
142+
static const struct clk_ops clk_half_divider_ops = {
143143
.recalc_rate = clk_half_divider_recalc_rate,
144144
.round_rate = clk_half_divider_round_rate,
145145
.set_rate = clk_half_divider_set_rate,
146146
};
147-
EXPORT_SYMBOL_GPL(clk_half_divider_ops);
148147

149148
/**
150149
* Register a clock branch.

‎drivers/clk/rockchip/clk-px30.c

Lines changed: 56 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -167,6 +167,10 @@ PNAME(mux_uart5_p) = { "clk_uart5_src", "clk_uart5_np5", "clk_uart5_frac" };
167167
PNAME(mux_cif_out_p) = { "xin24m", "dummy_cpll", "npll", "usb480m" };
168168
PNAME(mux_dclk_vopb_p) = { "dclk_vopb_src", "dclk_vopb_frac", "xin24m" };
169169
PNAME(mux_dclk_vopl_p) = { "dclk_vopl_src", "dclk_vopl_frac", "xin24m" };
170+
PNAME(mux_nandc_p) = { "clk_nandc_div", "clk_nandc_div50" };
171+
PNAME(mux_sdio_p) = { "clk_sdio_div", "clk_sdio_div50" };
172+
PNAME(mux_emmc_p) = { "clk_emmc_div", "clk_emmc_div50" };
173+
PNAME(mux_sdmmc_p) = { "clk_sdmmc_div", "clk_sdmmc_div50" };
170174
PNAME(mux_gmac_p) = { "clk_gmac_src", "gmac_clkin" };
171175
PNAME(mux_gmac_rmii_sel_p) = { "clk_gmac_rx_tx_div20", "clk_gmac_rx_tx_div2" };
172176
PNAME(mux_rtc32k_pmu_p) = { "xin32k", "pmu_pvtm_32k", "clk_rtc32k_frac", };
@@ -460,16 +464,40 @@ static struct rockchip_clk_branch px30_clk_branches[] __initdata = {
460464
/* PD_MMC_NAND */
461465
GATE(HCLK_MMC_NAND, "hclk_mmc_nand", "hclk_peri_pre", 0,
462466
PX30_CLKGATE_CON(6), 0, GFLAGS),
463-
COMPOSITE(SCLK_NANDC, "clk_nandc", mux_gpll_cpll_npll_p, 0,
467+
COMPOSITE(SCLK_NANDC_DIV, "clk_nandc_div", mux_gpll_cpll_npll_p, 0,
464468
PX30_CLKSEL_CON(15), 6, 2, MFLAGS, 0, 5, DFLAGS,
469+
PX30_CLKGATE_CON(5), 11, GFLAGS),
470+
COMPOSITE(SCLK_NANDC_DIV50, "clk_nandc_div50", mux_gpll_cpll_npll_p, 0,
471+
PX30_CLKSEL_CON(15), 6, 2, MFLAGS, 8, 5, DFLAGS,
472+
PX30_CLKGATE_CON(5), 12, GFLAGS),
473+
COMPOSITE_NODIV(SCLK_NANDC, "clk_nandc", mux_nandc_p,
474+
CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
475+
PX30_CLKSEL_CON(15), 15, 1, MFLAGS,
465476
PX30_CLKGATE_CON(5), 13, GFLAGS),
466477

467-
COMPOSITE(SCLK_SDIO, "clk_sdio", mux_gpll_cpll_npll_xin24m_p, 0,
478+
COMPOSITE(SCLK_SDIO_DIV, "clk_sdio_div", mux_gpll_cpll_npll_xin24m_p, 0,
468479
PX30_CLKSEL_CON(18), 14, 2, MFLAGS, 0, 8, DFLAGS,
480+
PX30_CLKGATE_CON(6), 1, GFLAGS),
481+
COMPOSITE_DIV_OFFSET(SCLK_SDIO_DIV50, "clk_sdio_div50",
482+
mux_gpll_cpll_npll_xin24m_p, 0,
483+
PX30_CLKSEL_CON(18), 14, 2, MFLAGS,
484+
PX30_CLKSEL_CON(19), 0, 8, DFLAGS,
485+
PX30_CLKGATE_CON(6), 2, GFLAGS),
486+
COMPOSITE_NODIV(SCLK_SDIO, "clk_sdio", mux_sdio_p,
487+
CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
488+
PX30_CLKSEL_CON(19), 15, 1, MFLAGS,
469489
PX30_CLKGATE_CON(6), 3, GFLAGS),
470490

471-
COMPOSITE(SCLK_EMMC, "clk_emmc", mux_gpll_cpll_npll_xin24m_p, 0,
491+
COMPOSITE(SCLK_EMMC_DIV, "clk_emmc_div", mux_gpll_cpll_npll_xin24m_p, 0,
472492
PX30_CLKSEL_CON(20), 14, 2, MFLAGS, 0, 8, DFLAGS,
493+
PX30_CLKGATE_CON(6), 4, GFLAGS),
494+
COMPOSITE_DIV_OFFSET(SCLK_EMMC_DIV50, "clk_emmc_div50", mux_gpll_cpll_npll_xin24m_p, 0,
495+
PX30_CLKSEL_CON(20), 14, 2, MFLAGS,
496+
PX30_CLKSEL_CON(21), 0, 8, DFLAGS,
497+
PX30_CLKGATE_CON(6), 5, GFLAGS),
498+
COMPOSITE_NODIV(SCLK_EMMC, "clk_emmc", mux_emmc_p,
499+
CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
500+
PX30_CLKSEL_CON(21), 15, 1, MFLAGS,
473501
PX30_CLKGATE_CON(6), 6, GFLAGS),
474502

475503
COMPOSITE(SCLK_SFC, "clk_sfc", mux_gpll_cpll_p, 0,
@@ -494,8 +522,16 @@ static struct rockchip_clk_branch px30_clk_branches[] __initdata = {
494522
/* PD_SDCARD */
495523
GATE(0, "hclk_sdmmc_pre", "hclk_peri_pre", 0,
496524
PX30_CLKGATE_CON(6), 12, GFLAGS),
497-
COMPOSITE(SCLK_SDMMC, "clk_sdmmc", mux_gpll_cpll_npll_xin24m_p, 0,
525+
COMPOSITE(SCLK_SDMMC_DIV, "clk_sdmmc_div", mux_gpll_cpll_npll_xin24m_p, 0,
498526
PX30_CLKSEL_CON(16), 14, 2, MFLAGS, 0, 8, DFLAGS,
527+
PX30_CLKGATE_CON(6), 13, GFLAGS),
528+
COMPOSITE_DIV_OFFSET(SCLK_SDMMC_DIV50, "clk_sdmmc_div50", mux_gpll_cpll_npll_xin24m_p, 0,
529+
PX30_CLKSEL_CON(16), 14, 2, MFLAGS,
530+
PX30_CLKSEL_CON(17), 0, 8, DFLAGS,
531+
PX30_CLKGATE_CON(6), 14, GFLAGS),
532+
COMPOSITE_NODIV(SCLK_SDMMC, "clk_sdmmc", mux_sdmmc_p,
533+
CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
534+
PX30_CLKSEL_CON(17), 15, 1, MFLAGS,
499535
PX30_CLKGATE_CON(6), 15, GFLAGS),
500536

501537
/* PD_USB */
@@ -763,29 +799,29 @@ static struct rockchip_clk_branch px30_clk_branches[] __initdata = {
763799
GATE(0, "pclk_ddrphy", "pclk_top_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(16), 3, GFLAGS),
764800
GATE(PCLK_MIPIDSIPHY, "pclk_mipidsiphy", "pclk_top_pre", 0, PX30_CLKGATE_CON(16), 4, GFLAGS),
765801
GATE(PCLK_MIPICSIPHY, "pclk_mipicsiphy", "pclk_top_pre", 0, PX30_CLKGATE_CON(16), 5, GFLAGS),
766-
GATE(PCLK_USB_GRF, "pclk_usb_grf", "pclk_top_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(16), 6, GFLAGS),
802+
GATE(PCLK_USB_GRF, "pclk_usb_grf", "pclk_top_pre", 0, PX30_CLKGATE_CON(16), 6, GFLAGS),
767803
GATE(0, "pclk_cpu_hoost", "pclk_top_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(16), 7, GFLAGS),
768804

769805
/* PD_VI */
770-
GATE(0, "aclk_vi_niu", "aclk_vi_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(4), 15, GFLAGS),
806+
GATE(0, "aclk_vi_niu", "aclk_vi_pre", 0, PX30_CLKGATE_CON(4), 15, GFLAGS),
771807
GATE(ACLK_CIF, "aclk_cif", "aclk_vi_pre", 0, PX30_CLKGATE_CON(5), 1, GFLAGS),
772808
GATE(ACLK_ISP, "aclk_isp", "aclk_vi_pre", 0, PX30_CLKGATE_CON(5), 3, GFLAGS),
773-
GATE(0, "hclk_vi_niu", "hclk_vi_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(5), 0, GFLAGS),
809+
GATE(0, "hclk_vi_niu", "hclk_vi_pre", 0, PX30_CLKGATE_CON(5), 0, GFLAGS),
774810
GATE(HCLK_CIF, "hclk_cif", "hclk_vi_pre", 0, PX30_CLKGATE_CON(5), 2, GFLAGS),
775811
GATE(HCLK_ISP, "hclk_isp", "hclk_vi_pre", 0, PX30_CLKGATE_CON(5), 4, GFLAGS),
776812

777813
/* PD_VO */
778-
GATE(0, "aclk_vo_niu", "aclk_vo_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(3), 0, GFLAGS),
814+
GATE(0, "aclk_vo_niu", "aclk_vo_pre", 0, PX30_CLKGATE_CON(3), 0, GFLAGS),
779815
GATE(ACLK_VOPB, "aclk_vopb", "aclk_vo_pre", 0, PX30_CLKGATE_CON(3), 3, GFLAGS),
780816
GATE(ACLK_RGA, "aclk_rga", "aclk_vo_pre", 0, PX30_CLKGATE_CON(3), 7, GFLAGS),
781817
GATE(ACLK_VOPL, "aclk_vopl", "aclk_vo_pre", 0, PX30_CLKGATE_CON(3), 5, GFLAGS),
782818

783-
GATE(0, "hclk_vo_niu", "hclk_vo_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(3), 1, GFLAGS),
819+
GATE(0, "hclk_vo_niu", "hclk_vo_pre", 0, PX30_CLKGATE_CON(3), 1, GFLAGS),
784820
GATE(HCLK_VOPB, "hclk_vopb", "hclk_vo_pre", 0, PX30_CLKGATE_CON(3), 4, GFLAGS),
785821
GATE(HCLK_RGA, "hclk_rga", "hclk_vo_pre", 0, PX30_CLKGATE_CON(3), 8, GFLAGS),
786822
GATE(HCLK_VOPL, "hclk_vopl", "hclk_vo_pre", 0, PX30_CLKGATE_CON(3), 6, GFLAGS),
787823

788-
GATE(0, "pclk_vo_niu", "pclk_vo_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(3), 2, GFLAGS),
824+
GATE(0, "pclk_vo_niu", "pclk_vo_pre", 0, PX30_CLKGATE_CON(3), 2, GFLAGS),
789825
GATE(PCLK_MIPI_DSI, "pclk_mipi_dsi", "pclk_vo_pre", 0, PX30_CLKGATE_CON(3), 9, GFLAGS),
790826

791827
/* PD_BUS */
@@ -940,7 +976,7 @@ static struct rockchip_clk_branch px30_clk_pmu_branches[] __initdata = {
940976
GATE(0, "pclk_cru_pmu", "pclk_pmu_pre", CLK_IGNORE_UNUSED, PX30_PMU_CLKGATE_CON(0), 8, GFLAGS),
941977
};
942978

943-
static const char *const px30_pmucru_critical_clocks[] __initconst = {
979+
static const char *const px30_cru_critical_clocks[] __initconst = {
944980
"aclk_bus_pre",
945981
"pclk_bus_pre",
946982
"hclk_bus_pre",
@@ -950,10 +986,16 @@ static const char *const px30_pmucru_critical_clocks[] __initconst = {
950986
"pclk_top_pre",
951987
"pclk_pmu_pre",
952988
"hclk_usb_niu",
989+
"pclk_vo_niu",
990+
"aclk_vo_niu",
991+
"hclk_vo_niu",
992+
"aclk_vi_niu",
993+
"hclk_vi_niu",
953994
"pll_npll",
954995
"usb480m",
955996
"clk_uart2",
956997
"pclk_uart2",
998+
"pclk_usb_grf",
957999
};
9581000

9591001
static void __init px30_clk_init(struct device_node *np)
@@ -985,6 +1027,9 @@ static void __init px30_clk_init(struct device_node *np)
9851027
&px30_cpuclk_data, px30_cpuclk_rates,
9861028
ARRAY_SIZE(px30_cpuclk_rates));
9871029

1030+
rockchip_clk_protect_critical(px30_cru_critical_clocks,
1031+
ARRAY_SIZE(px30_cru_critical_clocks));
1032+
9881033
rockchip_register_softrst(np, 12, reg_base + PX30_SOFTRST_CON(0),
9891034
ROCKCHIP_SOFTRST_HIWORD_MASK);
9901035

@@ -1017,9 +1062,6 @@ static void __init px30_pmu_clk_init(struct device_node *np)
10171062
rockchip_clk_register_branches(ctx, px30_clk_pmu_branches,
10181063
ARRAY_SIZE(px30_clk_pmu_branches));
10191064

1020-
rockchip_clk_protect_critical(px30_pmucru_critical_clocks,
1021-
ARRAY_SIZE(px30_pmucru_critical_clocks));
1022-
10231065
rockchip_clk_of_add_provider(np, ctx);
10241066
}
10251067
CLK_OF_DECLARE(px30_cru_pmu, "rockchip,px30-pmucru", px30_pmu_clk_init);

‎include/dt-bindings/clock/px30-cru.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -85,6 +85,8 @@
8585
#define SCLK_EMMC_DIV50 83
8686
#define SCLK_DDRCLK 84
8787
#define SCLK_UART1_SRC 85
88+
#define SCLK_SDMMC_DIV 86
89+
#define SCLK_SDMMC_DIV50 87
8890

8991
/* dclk gates */
9092
#define DCLK_VOPB 150

0 commit comments

Comments
 (0)